Frequency synthesizer with injection locked oscillator

Patent metadata

Field	Value
Publication number	US-9998128-B2
Application number	US-201514681455-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 8, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.

First claim

What is claimed is:

1. A ring oscillator circuit, comprising:
a plurality of inverters; and
a plurality of multiplexers, a multiplexer coupled to an output of each inverter at a first input of the multiplexer and an inverter coupled to an output of each multiplexer at an input of the inverter,
each multiplexer arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when an enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state, wherein the reference signal comprises a periodic pulse signal having a rising edge and a falling edge on each pulse, one of the rising edge or the falling edge replacing an edge of the oscillation signal at an output of a multiplexer when the enable signal received at the multiplexer is in the first state.

2. The ring oscillator circuit of claim 1 , wherein the plurality of inverters and the plurality of multiplexers are arranged in a loop and generate the oscillation signal, and wherein the loop is opened at periodic intervals and an edge of the reference signal replaces an edge of the oscillation signal at the intervals.

3. The ring oscillator circuit of claim 2 , wherein the replacement of the edge of the reference signal for the edge of the oscillation signal adjusts a timing of the oscillation signal.

4. The ring oscillator circuit of claim 1 , wherein an enable signal at a first multiplexer of the plurality of multiplexers and an enable signal at a second multiplexer of the plurality of multiplexers are not in the first state simultaneously.

5. The ring oscillator circuit of claim 1 , wherein at least one enable signal received at a multiplexer is activated to the first state at every cycle of the reference signal.

6. The ring oscillator circuit of claim 1 , wherein the multiplexers of the plurality of multiplexers are subsequently enabled at a frequency comprising a combination of an integer multiplication factor and a fractional multiplication factor of a frequency of the reference signal.

7. The ring oscillator circuit of claim 6 , wherein the multiplexers of the plurality of multiplexers are enabled in an order that is not sequential to an order of their electrical coupling within the circuit.

8. A phase-locked loop (PLL) system, comprising:
a multi-stage ring oscillator circuit, including a plurality of inverters and a plurality of multiplexers alternately coupled in a loop, a multiplexer coupled to an output of each inverter at a first input of the multiplexer and an inverter coupled to an output of each multiplexer at an input of the inverter; and
a digital control module arranged to enable each of the plurality of multiplexers via an enable signal according to a predetermined pattern, each multiplexer arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when the enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state.

9. The PLL system of claim 8 , further comprising a plurality of phase detectors, a phase detector coupled to the output of each inverter and to the reference signal and arranged to detect a phase difference between the oscillation signal and the reference signal and to feed back a difference signal to the digital control module based on the detecting.

10. The PLL system of claim 9 , further comprising a cycle counter coupled to an output of one of the multiplexers and arranged to count a quantity of cycles of the multi-stage ring oscillator circuit and to output a result signal to the digital control module based on the counting.

11. The PLL system of claim 9 , further comprising a loop filter arranged to receive an aggregate signal including a frequency control signal and feedback from the multi-stage ring oscillator circuit and to tune a frequency of the multi-stage ring oscillator circuit based on the aggregate signal.

12. The PLL system of claim 11 , wherein the frequency control signal comprises an accumulated signal based on a frequency control word and the feedback includes a phase error between the oscillation signal and the reference signal, and wherein the aggregate signal includes the phase error subtracted from the frequency control signal.

13. The PLL system of claim 9 , further comprising an injection controller arranged to determine which phase of the multi-stage ring oscillator circuit to enable a multiplexer of the plurality of multiplexers via the enable signal according to the predetermined pattern.

14. The PLL system of claim 9 , wherein the digital control module is comprised of digital components clocked via the reference signal.

15. The PLL system of claim 9 , wherein the multi-stage ring oscillator circuit comprises a digitally controlled ring oscillator (DCRO) and includes a tuning matrix of inverter stages coupled in parallel to the plurality of inverters to drive a frequency of the multi-stage ring oscillator circuit to a desired frequency value.

16. The PLL system of claim 9 , wherein the multi-stage ring oscillator circuit comprises an analog voltage controlled oscillator (VCO).

17. A method, comprising:
alternately coupling a plurality of inverters and a plurality of multiplexers in a loop, such that a multiplexer is coupled to an output of each inverter at a first input of the multiplexer and an inverter is coupled to an output of each multiplexer at an input of the inverter;
receiving a reference signal at a second input of each of the plurality of multiplexers;
outputting, from a multiplexer, the reference signal when an enable signal received at the multiplexer is in a first state; and
outputting, from the multiplexer, an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state, wherein the reference signal comprises a periodic pulse signal having a rising edge and a falling edge on each pulse, one of the rising edge or the falling edge replacing an edge of the oscillation signal at an output of a multiplexer when the enable signal received at the multiplexer is in the first state.

18. The method of claim 17 , further comprising independently enabling each multiplexer of the plurality of multiplexers via the enable signal according to a predetermined frequency comprising a combination of an integer multiplication factor and a fractional multiplication factor of a frequency of the reference signal.

19. The method of claim 18 , further comprising generating the oscillation signal via the plurality of inverters and the plurality of multiplexers in the loop, and reducing jitter of the oscillation signal by opening the loop and replacing an edge of the oscillation signal by an edge of the reference signal according to the predetermined frequency.

20. The method of claim 18 , further comprising generating the oscillation signal via the plurality of inverters and the plurality of multiplexers in the loop, and adjusting a resolution of a frequency of the oscillation signal by adjusting the predetermined frequency and opening the loop and replacing an edge of the oscillation signal by an edge of the reference signal according to the adjusted predetermined frequency.

21. The method of claim 18 , further comprising generating the oscillation signal via the plurality of inverters and the plurality of mult

Assignees

• Infineon Technologies Ag

Inventors

• Grollitsch Werner

Classifications

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title