Method and apparatus of dead time tuning in an inverter

Patent metadata

Field	Value
Publication number	US-10468974-B2
Application number	US-201916254633-A
Country	US
Kind code	B2
Filing date	Jan 23, 2019
Priority date	Mar 15, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method that prevents overload to input source and reduces parasitic inductance in an inverter circuit with dead-time control. A sensing capacitor senses temperatures of transistors in the inverter circuit. A delay generator changes delay times in response to receiving the temperatures of the transistors from the sensing capacitor. A dead time generation unit changes the dead times for the transistors in response to changes in the delay times.

First claim

What is claimed is:

1. A method that prevents overload to input source and reduces parasitic inductance in an inverter circuit with dead-time control, the method comprising:
sensing, with a first sensing capacitor, temperatures of a high side device in the inverter circuit;
sensing, with a second sensing capacitor, temperatures of a low side device in the inverter circuit;
changing, by a first delay generator and in response to receiving the temperatures from the first sensing capacitor, first dead time intervals that correspond to dead times before the high side device is turned on;
changing, by a second delay generator and in response to receiving the temperatures from the second sensing capacitor, second dead time intervals that correspond to dead times before the low side device is turned on; and
preventing overload to the input source and reducing parasitic inductance by connecting the first sensing capacitor between an output of the first delay generator and a ground, and connecting the second sensing capacitor between an output of the second delay generator and the ground,
wherein the deadtime control includes generating dead times based on the first dead time intervals and the second dead time intervals.

2. The method of claim 1 further comprising:
changing capacitances of the first sensing capacitor in response to sensing the temperatures of the high side device; and
changing capacitances of the second sensing resistor in response to sensing the temperatures of the low side device.

3. The method of claim 1 further comprising:
changing first delay times generated from the first delay generator in response to changes in capacitances of the first sensing capacitor; and
changing second delay times generated from the second delay generator in response to changes in capacitances of the second sensing capacitor.

4. The method of claim 1 , wherein a first fixed value resistor is connected between an input and the output of the first delay generator, and a second fixed value resistor is connected between an input and the output of the second delay generator.

5. The method of claim 1 , wherein the first sensing capacitor includes a first negative temperature coefficient capacitor and a first positive temperature coefficient capacitor that are serially connected, the second sensing resistor includes a second negative temperature coefficient capacitor and a second positive temperature coefficient capacitor that are serially connected.

6. The method of claim 5 , wherein the first negative temperature coefficient capacitor has a dielectric permittivity

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the first positive temperature coefficient capacitor has a dielectric permittivity ε 0 ε c2 =e α 1 (T−T C ) , where T is the temperatures of the high side device, T C is a Curie temperature, α 1 is a constant value, A, B and C are Steinhart-Hart coefficients, ε 0 is vacuum permittivity.

7. The method of claim 1 further comprising:
connecting the first delay generator with the first sensing capacitor by one conductor strip only, and
connecting the second delay generator with the second sensing capacitor by one conductor strip only.

8. An inverter circuit that prevents overload to input source and reduces parasitic inductance in the inverter circuit, comprising:
a first sensing capacitor that is thermally connected to a high side device in the inverter circuit;
a second sensing capacitor that is thermally connected to a low side device in the inverter circuit;
a dead times generation unit that prevents shoot-through currents and reduces body-diode conduction time by generating dead times including first dead time intervals and second dead time intervals for the high side device and the low side device respectively and includes:
a first delay generator that changes the first dead time intervals, wherein the first sensing capacitor is connected between an output of the first delay generator and a ground; and
a second delay generator that changes the second dead time intervals, wherein the second sensing capacitor is connected between an output of the second delay generator and the ground,
wherein the first dead time intervals correspond to dead times before the high side device is turned on, and the second dead time intervals that correspond to dead times before the low side device is turned on.

9. The inverter circuit of claim 8 , wherein a first fixed value resistor is connected between an input and the output of the first delay generator; and a second fixed value resistor is connected between an input and the output of the second delay generator.

10. The inverter circuit of claim 8 , wherein the first delay generator electronically connects to the first sensing capacitor by only one conductor strip, and the second delay generator electronically connects to the second sensing capacitor by only one conductor strip.

11. The inverter circuit of claim 8 , wherein the first sensing capacitor includes a first negative temperature coefficient capacitor and a first positive temperature coefficient capacitor that are serially connected, the second sensing resistor includes a second negative temperature coefficient capacitor and a second positive temperature coefficient capacitor that are serially connected.

12. The inverter circuit of claim 11 , wherein the second negative temperature coefficient capacitor has a dielectric permittivity

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Assignees

• Hong Kong Applied Science & Tech Research Inst Co Ltd

Inventors

• Lee Hang Sang
• Liu Yan

Classifications

• H03K17/0822

  in field-effect transistor switches · CPC title

• H03K2017/0806

  against excessive temperature · CPC title

• H02M7/53871

  with automatic control of output voltage or current · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H03K17/04206

  in field-effect transistor switches · CPC title