DC-DC converter with temperature, process and voltage compensated dead time delay

Patent metadata

Field	Value
Publication number	US-9548654-B2
Application number	US-201514634922-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Oct 27, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature.

First claim

What is claimed is:

1. A delay circuit for providing a dead time delay to operate a driver transistor of a switching DC to DC conversion system, the delay circuit comprising:
a first inverter circuit, comprising:
a first transistor having a source terminal coupled with a regulated voltage node, a gate terminal coupled with a delay input node to receive a delay circuit input voltage signal, and a drain terminal coupled with a first inverter output node, and
a second transistor having a drain terminal coupled with the first inverter output node, a gate terminal coupled with the delay input node, and a source terminal coupled with a constant voltage node;

a diode-connected MOS transistor coupled to provide an impedance between the first inverter circuit and a first one of the regulated voltage node and the constant voltage node;
a MOS capacitor coupled between the first inverter output node and the first one of the regulated voltage node and the constant voltage node, the MOS capacitor and the diode-connected MOS transistor establishing a first inverter delay for the first inverter circuit;
a second inverter circuit, comprising:
a third transistor having a source terminal coupled with a first compensated voltage node, a gate terminal coupled with the first inverter output node, and a drain terminal coupled with a second inverter output node, and
a fourth transistor having a drain terminal coupled with the second inverter output node, a gate terminal coupled with the first inverter output node, and a source terminal coupled with the constant voltage node; and

an output inverter circuit, comprising:
a fifth transistor having a source terminal coupled with a supply voltage node, a gate terminal coupled with the second inverter output node, and a drain terminal coupled with a delay circuit output node, and
a sixth transistor having a drain terminal coupled with the delay circuit output node, a gate terminal coupled with the second inverter output node, and a source terminal coupled with the constant voltage node; and

a supply circuit providing a voltage at the first compensated voltage node which decreases with increasing temperature.

2. The delay circuit of claim 1 :
wherein a voltage at the supply voltage node is greater than a voltage at the regulated voltage node;
wherein the voltage at the regulated voltage node is greater than the voltage at the first compensated voltage node; and
wherein the delay circuit comprises a level shifting circuit coupled to receive an output signal from the second inverter output node and to provide an output signal to the gate terminals of the output inverter circuit transistors.

3. The delay circuit of claim 2 , wherein the level shifting circuit comprises:
a third inverter output node coupled directly or indirectly with the gate terminals of the output inverter circuit transistors;
a seventh transistor having a source terminal coupled with a second compensated voltage node, a gate terminal coupled with the second inverter output node, and a drain terminal coupled with the third inverter output node; and
an eighth transistor having a drain terminal coupled with the third inverter output node, a gate terminal coupled with the second inverter output node, and a source terminal coupled with the constant voltage node;
wherein the supply circuit provides a voltage at the second compensated voltage node greater than the voltage at the first compensated voltage node; and
wherein the voltage at the second compensated voltage node decreases with increasing temperature.

4. The delay circuit of claim 3 , wherein the supply circuit comprises:
a first circuit branch including a resistor and a first circuit branch transistor controlled by a reference voltage to provide a first current signal which increases with increasing temperature;
a first current mirror circuit, comprising: an input transistor coupled to receive the first current signal from the first current branch, and an output providing a second current signal and a third current signal proportional to the first current signal;
a second circuit branch coupled with the first current mirror circuit to receive the second current signal, the second circuit branch comprising:
a second circuit branch transistor having at least one terminal connected to a first internal node, and
a temperature compensation circuit coupled in series with the second circuit branch transistor between the output of the first current mirror circuit and the constant voltage node, the temperature compensation circuit comprising at least one diode-connected transistor operable when conducting the second current signal to provide a voltage drop across the temperature compensation circuit which decreases with increasing temperature to at least partially counteract increases of the second current signal with increasing temperature to provide a temperature compensated voltage at the first internal node;

a first output transistor having a gate terminal coupled with the first internal node and operable to generate the voltage at the regulated voltage node;
a second current mirror circuit comprising: an input transistor coupled to receive the third current signal from the first current mirror circuit, and an output providing a fourth current signal proportional to the third current signal;
a third circuit branch coupled with the second current mirror circuit to receive the fourth current signal, the third circuit branch comprising a third circuit branch transistor, a first resistance, and a second resistance coupled in series with one another between the supply voltage node and the second current mirror circuit, the third circuit branch transistor having a gate terminal coupled with the second circuit branch and at least one terminal connected to the first internal node;
a second output transistor having a gate terminal coupled with the first resistance of the third circuit branch and operable to generate the voltage at the first compensated voltage node which decreases with increasing temperature; and
a third output transistor having a gate terminal coupled with the second resistance of the third circuit branch and operable to generate the voltage at the second compensated voltage node which decreases with increasing temperature.

5. The delay circuit of claim 2 , wherein the level shifting circuit comprises a plurality of CMOS inverter circuits including a first CMOS inverter circuit coupled to receive the output signal from the second inverter output node and to provide an output signal to a succeeding CMOS inverter, and a final CMOS inverter circuit coupled to provide an output signal to the gate terminals of the output inverter circuit transistors; wherein each CMOS inverter circuit of the level shifting circuit includes a transistor coupled with a corresponding compensated voltage node at a voltage greater than a voltage of the compensated voltage node of the preceding inverter circuit; and wherein the voltage at each compensated voltage node decreases with increasing temperature.

6. The delay circuit of claim 5 , wherein the supply circuit comprises:
a first circuit branch including a resistor and a first circuit branch transistor controlled by a reference voltage to provide a first current signal which increases with increasing temperature;
a first current mirror circuit, comprising: an input transistor coupled to receive the first current signal from the first current branch, and an output providing a second current signal and a third current signal proportional to the first current signal;
a second circuit branch coupled with the first current mirror circuit to receive the second current signal, the second circuit branch comprising:
a second circuit branch transistor having at least one terminal connected to a firs

Assignees

• Texas Instruments Inc

Inventors

• Yi Jun
• Ou Xuechun

Classifications

• G05F3/267

  using both bipolar and field-effect technology · CPC title

• H03K2005/00143

  Avoiding variations of delay due to temperature · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M2001/385

  Electricity · mapped topic

• H03K5/134

  with field-effect transistors · CPC title