Circuit board, optoelectronic component and arrangement of optoelectronic components
US-9763330-B2 · Sep 12, 2017 · US
US10468569B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10468569-B2 |
| Application number | US-201615574385-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 19, 2016 |
| Priority date | May 15, 2015 |
| Publication date | Nov 5, 2019 |
| Grant date | Nov 5, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method of producing at least one connection carrier includes: A) providing a carrier plate with a planar top face; B) applying at least one electrically insulating insulation strip to the top face and cohesively connecting the carrier plate and the insulation strip; and C) applying at least one electrically conductive conductor strip to an adhesive surface of the insulation strip and cohesively connecting the insulation strip and the conductor strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip.
Opening claim text (preview).
The invention claimed is: 1. A method of producing at least one connection carrier, comprising: A) providing a carrier plate with a planar top face, C) applying at least one electrically conductive conductor strip to an adhesive surface of an insulation strip and cohesively connecting the insulation strip and the conductor strip, and B) applying at least one electrically insulating insulation strip to the planar top face and cohesively connecting the carrier plate and the insulation strip, wherein the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip, and the insulation strip and the conductor strip are applied jointly to the carrier plate. 2. The method according to claim 1 , wherein the cohesive connection in step B) and/or the cohesive connection in step C) is performed using a laminating process and/or an adhesive bond. 3. The method according to claim 1 , wherein step A) and step C) and, optionally, step B) are performed using a reel-to-reel process. 4. The method according to claim 1 , wherein prior to step B) a multiplicity of recesses is introduced into the carrier plate, and the application in step C) proceeds such that the conductor strip covers over at least one of the recesses at least in places in a covered-over region of the recess. 5. The method according to claim 1 , wherein, after step C), in a further step D), a region of the conductor strip and a region of the insulation strip are folded over in the covered-over region of the recess, the folded-over region of the conductor strip and the folded-over region of the insulation strip are then arranged on a side, remote from the carrier plate, of the non-folded-over region of the conductor strip, and after folding-over, the conductor strip is covered up at the covered-over region of the recess by the folded-over region of the insulation strip. 6. A connection carrier for electronic components, comprising: a carrier plate with a planar top face, at least one electrically insulating insulation strip applied to the top face, and at least one electrically conductive conductor strip applied to an adhesive surface, remote from the top face, of the insulation strip, wherein the carrier plate and the insulation strip and the insulation strip and the conductor strip are in each case cohesively connected, the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip, the carrier plate is of multilayer configuration and comprises a base plate, a dielectric multilayer system and, optionally, a metallic reflective layer, and the top face of the carrier plate has a reflectivity of at least 80% and at a wavelength of at least 430 nm and at most 700 nm. 7. The connection carrier according to claim 6 , wherein the connection carrier is not connectable using surface mounting (SMT). 8. The connection carrier according to claim 6 , wherein the insulation strip covers the entire top face, and the insulation strip is transparent. 9. The connection carrier according to claim 6 , wherein the carrier plate is of multilayer configuration and comprises the base plate and a transparent coating, which is electrically insulating, and an outer face, remote from the base plate, of the transparent coating forms the top face of the carrier plate. 10. The connection carrier according to claim 6 , wherein a region of the conductor strip and a region of the insulation strip is folded over in the region of the pockets, the folded-over region of the conductor strip and the folded-over region of the insulation strip are arranged on a side, remote from the carrier plate, of the non-folded-over region of the conductor strip, and the non-folded-over region of the conductor strip is covered in the region of the pockets by the folded-over region of the insulation strip. 11. The connection carrier according to claim 6 , wherein an insulation strip is associated one-to-one with each conductor strip, and the top face is of simply connected configuration. 12. The connection carrier according to claim 6 , wherein the at least one conductor strip has a length (L) and a width (B), the width of the conductor strip amounts to at most 20% of the length of the conductor strip, and along its length, the conductor strip covers at least 90% of the carrier plate and over its width at least 5% and at most 20% of the carrier plate. 13. The connection carrier according to claim 12 , wherein the at least one insulation strip has a length and a width, the length of the insulation strip amounts to at least the length of the conductor strip, and the width of the insulation strip amounts to at least 100 m more than the width of the conductor strip and/or the width of the insulation strip corresponds to at least 1.25 times the width of the conductor strip. 14. The connection carrier according to claim 6 , wherein side faces of the carrier plate comprise a multiplicity of pockets formed by notches in the carrier plate and at least one of the pockets is covered over at least in part by the conductor strip. 15. The connection carrier according to claim 14 , wherein the side faces of the carrier plate are covered at least in the region of the pockets at least in part with an insulation layer. 16. An optoelectronic semiconductor component comprising: the connection carrier according to claim 6 , and at least one optoelectronic semiconductor chip with connection points, wherein the at least one semiconductor chip is applied to a mounting surface of the carrier plate in a mounting region of the connection carrier, and at least one connection point electrically conductively connects with the at least one conductor strip. 17. The optoelectronic semiconductor component according to claim 16 , wherein the connection carrier comprises at least two conductor strips electrically insulated from the carrier plate by the at least one insulation strip, and each connection point electrically conductively connects with at least one conductor strip. 18. A connection carrier for electronic components, comprising: a carrier plate with a planar top face, at least one electrically insulating insulation strip applied to the top face, and at least one electrically conductive conductor strip applied to an adhesive surface, remote from the top face, of the insulation strip, wherein the carrier plate and the insulation strip and the insulation strip and the conductor strip are in each case cohesively connected, the conductor strip and the carrier plate are electrically insulated from one another by the insulation strip, and the connection carrier is not connectable using surface mounting (SMT).
batch processes · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title
Package configurations · CPC title
having particular electrical or magnetic properties, e.g. piezoelectric · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.