Contacting source and drain of a transistor device

Patent metadata

Field	Value
Publication number	US-10468300-B2
Application number	US-201715641927-A
Country	US
Kind code	B2
Filing date	Jul 5, 2017
Priority date	Jul 5, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.

First claim

What is claimed:

1. A method of manufacturing a semiconductor device, comprising:
forming raised source and drain regions on a semiconductor layer;
forming a first insulating layer over said semiconductor layer;
forming a first contact to one of said raised source and drain regions in said first insulating layer;
forming a second insulating layer over and above said first contact after forming said first contact;
forming a trench in said second insulating layer to remove a portion of said second insulating layer and expose said first contact, wherein said forming of said trench in said second insulating layer comprises a first reactive ion etching;
performing a first etching process through said trench to remove a portion of said first contact exposed below said trench, thereby forming a recessed surface of said first contact lower than an uppermost surface of said first contact, wherein said first etching process comprises a second reactive ion etching;
removing a portion of said first insulating layer exposed by said trench to form a recess in said first insulating layer, said recess exposing a portion of a sidewall of said first contact below said recessed surface of said first contact, wherein said removing of said portion of said first insulating layer comprises a third reactive ion etching; and
filling said trench and said recess formed in said trench with a contact material to form a second contact in contact with said first contact.

2. The method of claim 1 , wherein said first contact is a trench silicide structure.

3. The method of claim 1 , wherein said semiconductor layer is a semiconductor fin of a FinFET.

4. The method of claim 1 , wherein said second contact is formed to directly contact said first contact.

5. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor fin and a second semiconductor fin on a semiconductor layer;
forming a first source or drain region in and on said first semiconductor fin and forming a second source or drain region in and on said second semiconductor fin;
forming a first trench silicide structure on said first source or drain region and forming a second trench silicide structure on said second drain or source region;
etching said first trench silicide structure to form a stepped first trench silicide structure with an exposed lower horizontal surface and an upper horizontal surface connected by an upper vertical surface, said lower horizontal surface connecting a lower vertical surface to said upper vertical surface of said stepped first trench silicide structure, and to etch a trench in said second trench silicide structure; and
forming a first contact contacting said lower horizontal surface, said upper vertical surface and a portion of said lower vertical surface of said stepped first trench silicide structure and forming a second contact in said trench of said second trench silicide structure.

6. The method of claim 5 , wherein said first contact directly contacts said lower horizontal surface, said upper vertical surface and said portion of said lower vertical surface of said stepped first trench silicide structure and further comprising forming a liner in said trench of said second silicide trench structure before forming said second contact in said trench of said second trench silicide structure.

7. The method of claim 5 , further comprising forming a first insulating layer over said first source or drain region and said second source or drain region and wherein said first and second silicide trench structures are formed in said first insulating layer and further comprising removing a portion of said first insulating layer to expose a portion of said lower vertical surface of said stepped first trench silicide structure before forming said first contact.

8. The method of claim 7 , further comprising forming a second insulating layer over said first insulating layer and forming a first trench in said second insulating layer over said first silicide trench structure and forming a second trench in said second insulating layer over said second trench structure before forming said first and second contacts.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Labonte Andre
• Liebmann Lars
• Chanemougame Daniel
• Park Chanro
• Cave Nigel
• Kamineni Vimal

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title