Image sensor with buried-channel drain (bcd) transistors
US-2016268335-A1 · Sep 15, 2016 · US
US10468248B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10468248-B2 |
| Application number | US-201715485232-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 12, 2017 |
| Priority date | Apr 12, 2016 |
| Publication date | Nov 5, 2019 |
| Grant date | Nov 5, 2019 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In various embodiments, a method is provided. The method may include forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer, and forming a second layer above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region.
Opening claim text (preview).
What is claimed is: 1. A method, comprising: forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer; and forming a second layer comprising electroactive material above the first layer using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region, wherein the second layer reacts to the electric field of the buried electrically charged region so as to undergo self-assembly so as to form a structured layer. 2. The method of claim 1 , wherein the first layer comprises an electrically insulating material or consists thereof. 3. The method of claim 2 , wherein forming the buried electrically charged region comprises doping the first layer; wherein the buried electrically charged region is a doped region of the first layer. 4. The method of claim 3 , wherein forming the buried electrically charged region comprises forming a space charge zone in such a way that the space charge zone defines the buried electrically charged region. 5. The method of claim 4 , further comprising: irradiating the first layer with electromagnetic radiation, at least one of heating the first layer or applying an electrical voltage to the first layer in such a way that the field strength of the electric field generated by the space charge zone is increased. 6. The method of claim 1 , wherein the first layer comprises an electrically semiconducting material or consists thereof. 7. The method of claim 1 , wherein forming the buried electrically charged region comprises forming the electrically charged region at a surface of a substrate and subsequently applying a cover layer on the surface of the substrate in order to bury the electrically charged region. 8. The method of claim 7 , wherein the substrate is a silicon wafer; and wherein the cover layer is an epitaxial silicon layer. 9. The method of claim 1 , wherein forming the second layer comprises applying dielectric particles in a structured fashion; wherein the dielectric particles partly adhere to the first layer on account of the electric field. 10. The method of claim 1 , wherein forming the second layer is carried out in such a way that the second layer masks the first layer; wherein a region of the first layer above the buried electrically charged region is free of the second layer. 11. The method of claim 10 , further comprising: doping the region of the first layer above the buried electrically charged region by using the second layer as masking layer. 12. The method of claim 1 , further comprising: forming a masking layer by using the second layer in such a way that the masking layer masks the first layer; wherein a region of the first layer above the buried electrically charged region is free of the masking layer. 13. The method of claim 12 , further comprising: doping that region of the first layer which is arranged above the buried electrically charged region by using the masking layer. 14. The method of claim 1 , wherein the structured layer comprises at least one through hole. 15. A method, comprising: forming a buried electrically charged region at a predefined position in a first layer in such a way that the buried electrically charged region generates an electric field having a lateral inhomogeneous field distribution above the first layer; and forming a second layer above the first layer based on and using the field distribution in such a way that a structure of the second layer correlates with the position of the buried electrically charged region, wherein forming the second layer comprises: determining the laterally inhomogeneous field distribution of the electric field; and forming the second layer using the determined field distribution. 16. The method of claim 15 , wherein forming the second layer comprises laser-assisted deposition using the determined field distribution.
Thermal treatments, e.g. annealing or sintering · CPC title
of masks comprising organic materials · CPC title
with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title
into Group IV semiconductors · CPC title
using masks · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.