Image sensor with buried-channel drain (bcd) transistors

Patent metadata

Field	Value
Publication number	US-2016268335-A1
Application number	US-201615052574-A
Country	US
Kind code	A1
Filing date	Feb 24, 2016
Priority date	Mar 9, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.

First claim

What is claimed is:

1 . An image sensor, comprising:
photosensitive elements that generates charge; and an output buffer circuit that receives the charge from the photosensitive elements and that includes a load transistor, wherein the load transistor includes a gate conductor and a buried-channel drain region that extends partially beneath the gate conductor.

2 . The image sensor of claim 1 , wherein the output buffer circuit includes a source-follow transistor coupled in series with the load transistor, and wherein the gate conductor of the load transistor receives a fixed bias voltage signal.

3 . The image sensor of claim 1 , wherein the gate conductor overlaps with at least a portion of the buried-channel drain region.

4 . The image sensor of claim 1 , wherein the buried-channel drain region has a first portion that is covered by the gate conductor and a second portion that is not covered by the gate conductor.

5 . The image sensor of claim 4 , wherein the first and second portions of the buried-channel region have different lengths.

6 . The image sensor of claim 5 , wherein the first and second portions of the buried-channel region have identical lengths.

7 . The image sensor of claim 5 , wherein the first and second portions of the buried-channel region have different dopant concentrations.

8 . The image sensor of claim 5 , wherein the first and second portions of the buried-channel region have identical dopant profiles.

9 . The image sensor of claim 1 , wherein the load transistor has a symmetrical source and drain transistor structure.

10 . The image sensor of claim 1 , wherein the load transistor has an asymmetric source and drain transistor structure.

11 . A method of fabricating a transistor on an image sensor, comprising:
forming photoresist on a substrate, wherein the photoresist has an opening; forming a buried-channel drain region through the opening in the photoresist; forming a gate liner on the substrate; and after forming the buried-channel drain region, forming a gate conductor that is on the gate liner and that extends at least partially over the buried-channel drain region.

12 . The method of claim 11 , wherein forming the buried-channel drain region comprises forming the buried-channel drain region by performing a first implant of a first concentration, the method further comprising:
performing a source-drain implant of a second concentration that is greater than the first concentration to form a drain region and a source region for the transistor.

13 . The method of claim 12 , further comprising:
forming additional photoresist on the substrate; forming a first opening in the additional photoresist having the same footprint as the drain region; and forming a second opening in the additional photoresist having a footprint that is larger than the source region.

14 . The method of claim 11 , wherein a first portion of the buried-channel drain region overlaps with the gate conductor, and wherein a second portion of the buried-channel drain region is non-overlapping with the gate conductor.

15 . The method of claim 11 , further comprising:
forming a buried-channel source region through another opening in the photoresist, wherein the buried-channel source region extends at least partially beneath the gate conductor.

16 . A method of fabricating a transistor on an image sensor, comprising:
forming a gate liner on the substrate; forming a gate conductor on the gate liner; forming photoresist on the gate conductor, wherein the photoresist has an opening; and forming a buried-channel drain region through the opening in the photoresist, wherein the buried-channel drain region extends at least partially under the gate conductor.

17 . The method of claim 16 , wherein forming the buried-channel drain region (BCD) comprises forming a first portion of the BCD region that is covered by the gate conductor and forming a second portion of the BCD region that is not covered by the gate conductor.

18 . The method of claim 16 , wherein forming the buried-channel drain region comprises forming the buried-channel drain region by performing a first implant of a first concentration, the method further comprising:
performing a source-drain implant of a second concentration that is greater than the first concentration to form a drain region and a source region.

19 . The method of claim 18 , further comprising:
forming additional photoresist on the substrate; forming a first opening in the additional photoresist having the same footprint as the drain region; and forming a second opening in the additional photoresist having a footprint that is larger than the source region.

20 . The method of claim 16 , further comprising:
forming a buried-channel source region through another opening in the photoresist, wherein the buried-channel source region also extends at least partially beneath the gate conductor.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Stevens Eric

Classifications

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H10D44/462

  Buried-channel CCD · CPC title

• H10D44/454

  Output structures · CPC title

• H10F39/1532

  Frame-interline transfer · CPC title

• H10F39/811

  Interconnections · CPC title