Display panel and method of driving the same

Patent metadata

Field	Value
Publication number	US-2016155409-A1
Application number	US-201514953614-A
Country	US
Kind code	A1
Filing date	Nov 30, 2015
Priority date	Dec 2, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

A display panel and a method of driving the same are disclosed. The display panel includes a shift register with a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines. Each stage includes a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween, a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and a node controller coupled to the first node, the second node, and the output node. In each stage, the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.

First claim

What is claimed is:

1 . A display device, comprising:
a display panel having a plurality of scan lines; a timing controller; and a scan driver comprising a plurality of scan stages configured to generate scan line signals for each of the plurality of scan lines, each of the plurality of scan stages comprising:
a pull-transistor and a pull-down transistor coupled in series and defining an output node for a corresponding one of the plurality scan lines,
a driver configured to generate driver control signals at a first gate electrode for the pull-up transistor and at a second gate electrode for the pull-down transistor, and
a node controller configured to selectively couple and decouple a reference voltage node to the first gate electrode, the second gate electrode, and the output node according to a control signal from the timing controller.

2 . The display device of claim 1 , wherein the control signal from the timing controller is configured to turn off devices in the node controller during a first time period to provide the decoupling, and wherein the control signal from the timing controller is configured to turn on the devices during a second time period to provide the coupling.

3 . The display device of claim 2 , wherein the devices are configured during the second time period to discharge the first gate electrode, the second gate electrode, and the output node with a delay.

4 . The display device of claim 2 , wherein the control signal from the timing controller is inverted to a voltage for turning on the one or more transistors at a start of the second time period.

5 . The display device of claim 2 , wherein the devices in the node controller comprise:
a first transistor connected in series between the first gate electrode and a reference voltage node; a second transistor connected in series between the second gate electrode and the reference voltage node; and a third transistor connected in series between the output node and the reference voltage node, wherein gate electrodes of the first, the second, and the third transistors are adapted to receive the control signal from the timing controller.

6 . The display device of claim 5 , wherein the devices in the node controller further comprise at least one fourth transistor connected in series between a portion of the driver and the reference voltage node, wherein the gate electrode of the at least one fourth transistor is adapted to receive the control signal from the timing controller.

7 . A method of operating a display device, comprising:
generating, at a timing controller, a control signal for a node controller configured to selectively couple and decouple a reference voltage node to a first gate electrode of a pull-up transistor of a scan driver stage, a second gate electrode of a pull-down transistor of the scan driver stage, and an output node of the scan driver stage, the generating comprising: during a first time period, configuring the control signal to decouple the reference voltage node from the first gate electrode, the second gate electrode, and the output node, and during a second time period after the first time period, configuring the control signal to couple the reference voltage node to the first gate electrode, the second gate electrode, and the output node.

8 . The method of claim 7 , wherein the node controller comprises one or more transistors connecting the reference voltage node to each of the first gate electrode, the second gate electrode, and the output node, and wherein the configuring during the second time period comprises:
during a first portion of the second time period, inverting the control signal to a voltage for turning on the one or more transistors, and during a second portion of the second time period, discharging the voltage for turning off the one or more transistors to a reference voltage with a delay.

9 . The method of claim 8 , wherein the discharging is completed prior to an end of the second time period.

10 . The method of claim 7 , further comprising:
detecting a change in an input voltage to the display device; inverting a discharge signal to a low logic voltage in response to the detecting; determining that the discharge signal is at the low logic voltage; and in response to the determining that the discharge signal is at the low logic voltage, discharging a plurality of voltage supply lines for the scan driver stage.

11 . The method of claim 10 , wherein the plurality of supply voltage lines comprise two or more high voltage supply lines, and wherein the discharging comprises discharging the two or more high voltage supply lines at different rates.

12 . The method of claim 7 , further comprising:
setting, during the first time period and in response to the detecting, a clock signal to the low logic voltage; setting the clock signal to a high logic voltage at a start of the second time period; and discharging the clock signal to a reference voltage during the second time period.

13 . The method of claim 7 , further comprising:
setting a reference voltage node to a high logic at a start of the second time period; and discharging the reference voltage node to the reference voltage during the second time period.

14 . A display device, comprising:
a shift register including a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines, wherein each of the plurality of stages comprises:
a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween;
a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and
a node controller coupled to the first node, the second node, and the output node,
wherein the pull-up transistor is configured to supply a high logic voltage at the output node in response to the driver supplying a turn-on voltage at the first node, wherein the pull-down transistor is configured to supply a low logic voltage at the output node in response to the driver supplying a turn-on voltage at the second node, and wherein the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.

15 . The display device of claim 14 , wherein the node controller comprises a first transistor connected between the first node and a reference voltage source, a second transistor connected between the second node and the reference voltage source, and a third transistor connected between the output terminal and the reference voltage source.

16 . The display device of claim 15 , wherein the turn-on voltage is between a high logic voltage and the low logic voltage and greater than a threshold voltage of each of the first, the second, and the third transistors.

17 . The display device of claim 15 , wherein the node controller further comprising at least one fourth transistor connected in series between an internal node of the driver and the reference voltage source.

18 . The display device of claim 14 , further comprising a timing controller for generating the control signal.

19 . The display device of claim 18 , wherein the timing controller is configured to generate the control signal to have a delay.

Assignees

• Lg Display Co Ltd

Inventors

• Jeoung Hun
• Yu Sanghee
• Cho Sunghyun
• Lee Bosun
• Kim Byoungwoo
• Chang Sungwook

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2330/027

  Arrangements or methods related to powering off a display · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title