Display panel having a node controller for discharging nodes in a scan driver and driving method thereof

Patent metadata

Field	Value
Publication number	US-9754551-B2
Application number	US-201514953614-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Dec 2, 2014
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A display panel and a method of driving the same are disclosed. The display panel includes a shift register with a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines. Each stage includes a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween, a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and a node controller coupled to the first node, the second node, and the output node. In each stage, the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.

First claim

What is claimed is:

1. A display device, comprising:
a display panel comprising a plurality of scan lines;
a timing controller; and
a scan driver comprising a plurality of scan stages configured to generate a scan pulse for each of the plurality of scan lines, each of the plurality of scan stages comprising:
a pull-up transistor and a pull-down transistor coupled in series and defining an output node for a corresponding one of the plurality scan lines;
a driver configured to generate driver control signals at a first gate electrode for the pull-up transistor and at a second gate electrode for the pull-down transistor during a first time period; and
a node controller configured to:
decouple a reference voltage node to the first gate electrode, the second gate electrode, and the output node according to a control signal from the timing controller during the first time period; and
couple the reference voltage node to the first gate electrode, the second gate electrode, and the output node according to the control signal during a second time period,

wherein the first time period comprises a scan period in which the scan pulse is supplied to each of the scan lines,
wherein the second time period comprises a blank time in which the scan pulse is not supplied between respective frame periods displaying the image on the display panel, and
wherein the blank time is varied according to an amount of motion in an input image data of the display device.

2. The display device of claim 1 , wherein:
the control signal from the timing controller is configured to turn off devices in the node controller during the first time period to provide the decoupling; and
the control signal from the timing controller is further configured to turn on the devices during the second time period to provide the coupling.

3. The display device of claim 2 , wherein the devices are configured, during the second time period, to discharge the first gate electrode, the second gate electrode, and the output node with a delay.

4. The display device of claim 2 , wherein:
the control signal from the timing controller is inverted to a voltage for turning on the one or more transistors at a start of the second time period, and
the voltage is between a gate low voltage and a gate high voltage.

5. The display device of claim 2 , wherein the devices in the node controller comprise:
a first transistor connected in series between the first gate electrode and a reference voltage node;
a second transistor connected in series between the second gate electrode and the reference voltage node; and
a third transistor connected in series between the output node and the reference voltage node,
wherein gate electrodes of the first, the second, and the third transistors are configured to receive the control signal from the timing controller.

6. The display device of claim 5 , wherein the devices in the node controller further comprise:
at least one fourth transistor connected in series between a portion of the driver and the reference voltage node,
wherein the gate electrode of the at least one fourth transistor is configured to receive the control signal from the timing controller.

7. A method of operating a display device, the method comprising:
generating, at a timing controller, a control signal for a node controller configured to selectively couple and decouple a reference voltage node to a first gate electrode of a pull-up transistor of a scan driver stage, a second gate electrode of a pull-down transistor of the scan driver stage, and an output node of the scan driver stage, the generating comprising:
during a first time period, configuring the control signal to decouple the reference voltage node from the first gate electrode, the second gate electrode, and the output node, and
during a second time period after the first time period, configuring the control signal to couple the reference voltage node to the first gate electrode, the second gate electrode, and the output node,
wherein the first time period comprises a scan period in which a scan pulse is supplied to each of the scan lines,
wherein the second time period comprises:
a blank time in which the scan pulse is not supplied between respective frame periods displaying the image on the display panel, and
a power-off sequence of the display device, and

wherein the blank time is varied according to an amount of motion in an input image data of the display device.

8. The method of claim 7 , wherein:
the node controller comprises one or more transistors connecting the reference voltage node to each of the first gate electrode, the second gate electrode, and the output node; and
the configuring during the second time period comprises:
during a first portion of the power-off sequence, inverting the control signal to a voltage for turning on the one or more transistors, the voltage being between a gate low voltage and a gate high voltage, and
during a second portion of the power-off sequence, discharging the voltage for turning off the one or more transistors to a reference voltage with a delay.

9. The method of claim 8 , wherein the discharging is completed prior to an end of the power-off sequence.

10. The method of claim 7 , further comprising:
detecting a change in an input voltage to the display device;
inverting a discharge signal to a low logic voltage in response to the detecting to start the power-off sequence;
determining that the discharge signal is at the low logic voltage; and
in response to the determining that the discharge signal is at the low logic voltage, discharging a plurality of voltage supply lines for the scan driver stage during the power-off sequence.

11. The method of claim 10 , wherein:
the plurality of supply voltage lines comprise two or more high voltage supply lines; and
the discharging comprises discharging the two or more high voltage supply lines at different rates during the power-off sequence.

12. The method of claim 7 , further comprising:
setting, during the first time period, a clock signal to the low logic voltage;
setting the clock signal to a high logic voltage at a start of the power-off sequence; and
discharging the clock signal to a reference voltage during the power-off sequence.

13. The method of claim 7 , further comprising:
setting a reference voltage node to a high logic at a start of the power-off sequence; and
discharging the reference voltage node to the reference voltage during the power-off sequence.

14. A display device, comprising:
a shift register including a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines, each of the plurality of stages comprising:
a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween;
a driver comprising:
a first node coupled to a gate electrode of the pull-up transistor; and
a second node coupled to a gate electrode of the pull-down transistor; and

a node controller coupled to the first node, the second node, and the output node,
wherein the pull-up transistor is configured to supply a high voltage at the output node in response to the driver supplying a turn-on voltage at the first node,
wherein the pull-down transistor is configured to supply a low voltage at the output node in response to the driver supplying a turn-on voltage at the second node,
wherein the node controller is configured to:
decouple a reference voltage node to the first gate electrode, the second gate electrode, and the output node according to a control signal during the first time period, and
couple t

Assignees

• Lg Display Co Ltd

Inventors

• Jeoung Hun
• Yu Sanghee
• Cho Sunghyun
• Lee Bosun
• Kim Byoungwoo
• Chang Sungwook

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title