Fabrication method of electronic module

Patent metadata

Field	Value
Publication number	US-10461002-B2
Application number	US-201715646695-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Sep 3, 2014
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.

First claim

What is claimed is:

1. A method for fabricating an electronic module, comprising the steps of:
providing a substrate having a plurality of electronic elements and a plurality of separation portions each formed between adjacent two of the electronic elements, wherein each of the electronic elements has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface;
disposing the substrate on a carrier, wherein the active surface of each of the electronic elements is disposed on the carrier;
after disposing the substrate on the carrier, removing each of the separation portions to form at least an opening in each of the separation portions, causing each of the electronic elements to have a side surface connecting the active and inactive surfaces thereof;
forming a strengthening layer in the openings of the separation portions and on the side surfaces of the electronic elements; and
singulating the electronic elements along the opening.

2. The method of claim 1 , wherein the separation portions have a width in a range of 10 um to 4 mm.

3. The method of claim 1 , wherein the strengthening layer is formed around the side surfaces of the electronic elements.

4. The method of claim 1 , wherein the strengthening layer is made of an insulating material.

5. The method of claim 1 , wherein the singulation path along the separation portions is less in width than the separation portions.

6. The method of claim 1 , wherein if a plurality of openings are formed in each of the separation portions, the singulation path along the separation portion is positioned between the openings of the separation portion.

7. The method of claim 1 , wherein the strengthening layer is further formed on the inactive surfaces of the electronic elements.

8. The method of claim 1 , before singulating the electronic elements, further comprising forming an RDL structure on the strengthening layer, the separation portion and the active surface of each of the electronic elements, wherein the RDL structure is electrically connected to the electrode pads of the electronic element.

9. The method of claim 1 , before singulating the electronic elements, further comprising forming an RDL structure on the strengthening layer and the active surface of each of the electronic elements, wherein the RDL structure is electrically connected to the electrode pads of the electronic element.

10. The method of claim 1 , further comprising forming a plurality of conductive elements on the active surface of each of the electronic elements, wherein the conductive elements are electrically connected to the electrode pads of the electronic element.

11. The method of claim 1 , after singulating the electronic elements, further comprising bonding each of the electronic elements to a packaging substrate via the active surface thereof.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Lu Chang-Lun
• Chen Shih-Ching

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title