Dynamic amplifier and chip using the same

Patent metadata

Field	Value
Publication number	US-10454435-B2
Application number	US-201715830355-A
Country	US
Kind code	B2
Filing date	Dec 4, 2017
Priority date	Dec 27, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.

First claim

What is claimed is:

1. A dynamic amplifier, comprising:
an input pair of transistors, receiving a pair of differential inputs Vip and Vin and further providing a first terminal, a second terminal and a third terminal;
a load circuit, providing a pair of differential outputs Vop and Von with the load circuit coupled to a common mode terminal;
a driver for amplification; and
a bypassing circuit, operative to decrease currents of the load circuit,
wherein:
the driver is coupled to the first terminal in an amplification phase;
in the amplification phase, the load circuit is coupled to the second terminal and the third terminal; and
the bypassing circuit is coupled to the second terminal and the third terminal during a bypass period within the amplification phase.

2. The dynamic amplifier as claimed in claim 1 , wherein:
the load circuit includes a pair of load capacitors connected at the common mode terminal; and
in the amplification phase, the load capacitors are separately coupled to the second terminal and the third terminal.

3. The dynamic amplifier as claimed in claim 2 , wherein:
the bypassing circuit includes a pair of bypass current sources operative to decrease currents of the load capacitors; and
the pair of bypass current sources are separately coupled to the second terminal and the third terminal during the bypass period within the amplification phase.

4. The dynamic amplifier as claimed in claim 3 , wherein:
the driver for amplification is a current source for amplification which is coupled to the first terminal in the amplification phase.

5. The dynamic amplifier as claimed in claim 3 , wherein:
the bypass current sources provide variable bypass currents.

6. The dynamic amplifier as claimed in claim 1 , wherein:
the bypass period covers the amplification phase entirely.

7. The dynamic amplifier as claimed in claim 1 , wherein:
the bypass period just partially covers the amplification phase.

8. The dynamic amplifier as claimed in claim 7 , wherein:
the bypass period is arranged when the amplification phase has been on for a while.

9. The dynamic amplifier as claimed in claim 4 , wherein:
sources of the transistors of the input pair are connected at the first terminal;
drains of the transistors of the input pair are regarded as the second terminal and the third terminal; and
gates of the transistors of the input pair receive the differential inputs Vin and Vip.

10. The dynamic amplifier as claimed in claim 9 , wherein:
the amplification phase ends when a predetermined common mode voltage difference, ΔVcm, for a common mode voltage of the differential outputs Vop and Von is achieved.

11. The dynamic amplifier as claimed in claim 10 , providing a gain that is equal to gm·ΔVcm/(I 1 −I 2 ·Tb/T_A), where:
gm is a transconductance of each transistor of the input pair;
the current source for amplification provides a current of 2·I 1 ;
the bypass current sources each provide a bypass current of I 2 ;
the amplification phase is T_A long; and
the bypass period is Tb long.

12. The dynamic amplifier as claimed in claim 9 , wherein:
the load capacitors are discharged in a reset phase prior to the amplification phase; and
the load capacitors are charged in the amplification phase.

13. The dynamic amplifier as claimed in claim 12 , wherein:
the common mode terminal is ground; and
the differential outputs Vop and Von are both pulled down to the ground in the reset phase.

14. The dynamic amplifier as claimed in claim 13 , wherein:
the differential outputs Vop and Von are raised in the amplification phase.

15. The dynamic amplifier as claimed in claim 12 , wherein:
the common mode terminal is a power source terminal; and
the differential outputs Vop and Von are both connected to the power source terminal in the reset phase.

16. The dynamic amplifier as claimed in claim 15 , wherein:
the differential outputs Vop and Von drop in the amplification phase.

17. The dynamic amplifier as claimed in claim 9 , wherein:
the load capacitors are pre-charged in a reset phase prior to the amplification phase; and
the load capacitors are discharged in the amplification phase.

18. The dynamic amplifier as claimed in claim 17 , wherein:
the common mode terminal is ground; and
the differential outputs Vop and Von are both connected to a power source terminal in the reset phase.

19. The dynamic amplifier as claimed in claim 18 , wherein:
the differential outputs Vop and Von drop in the amplification phase.

20. The dynamic amplifier as claimed in claim 1 , wherein:
the differential outputs Vop and Von are sampled in a sample phase after the amplification phase.

21. A chip, comprising:
the dynamic amplifier as claimed in claim 1 ;
a front-stage circuit, transmitting the differential inputs Vip and Vin to the dynamic amplifier; and
a back-stage circuit, receiving the differential outputs Vop and Von from the dynamic amplifier.

22. The chip as claimed in claim 21 , further comprising:
a register for setting a decreased amount of current that the bypassing circuit caused on the load circuit.

23. The chip as claimed in claim 21 , further comprising:
a register for arranging the bypass period for the dynamic amplifier.

Assignees

• Mediatek Inc

Inventors

• Liu Chun-Cheng

Classifications

• H03F2203/45726

  the LC comprising more than one switch, which are not cross coupled · CPC title

• H03F2203/45634

  the LC comprising one or more switched capacitors · CPC title

• H03F2203/45648

  the LC comprising two current sources, which are not cascode current sources · CPC title

• H03F2203/45631

  the LC comprising one or more capacitors, e.g. coupling capacitors · CPC title

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title