BEOL vertical fuse formed over air gap

Patent metadata

Field	Value
Publication number	US-10453793-B2
Application number	US-201816053282-A
Country	US
Kind code	B2
Filing date	Aug 2, 2018
Priority date	Feb 23, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

First claim

What is claimed is:

1. A method of forming an electrical device comprising:
forming an array of metal lines, wherein at least one set of adjacent metal lines in said array of metal lines includes an air gap positioned therebetween;
forming a first plurality of trench structures to a depth to open the air gap;
forming a second plurality of trench structures to a depth that does not communicate with the air gap; and
forming a conductive material within the trenches, wherein the conductive material deposited in the open air gap provides a vertical fuse, and the portion of the conductive material formed in the plurality of trench structures that do not communicate with the air gap provide interconnect structures.

2. The method of claim 1 , wherein forming said array of metal lines comprises:
depositing an intralevel dielectric layer on a substrate;
forming a plurality of line trenches in the intralevel dielectric layer;
filling said plurality of line trenches with a metal to provide the array of metal lines; and
recessing the interlevel dielectric layer.

3. The method of claim 2 , wherein forming the air gap comprises:
depositing a dielectric cap atop and within the space separating adjacent metal lines within the array of metal lines, wherein a thickness of the dielectric cap pinches off within the space separating said adjacent metal lines to substantially enclose said air gap.

4. The method of claim 3 , wherein said forming the plurality of trenches in the interlevel dielectric layer comprises forming a first trench having a first depth portion and a second depth portion, wherein the second depth portion extends to said opened air gap, and forming a second trench having said first depth portion.

5. The method of claim 4 , wherein the second trench does not have a second depth portion.

6. The method of claim 4 , wherein the first depth portion provides a metal line.

7. The method of claim 6 , wherein the second depth portion provides vias.

8. The method of claim 7 , wherein said vias filled with the electrically conductive material provide a first contact region and a second contact region to the vertical fuse.

9. The method of claim 8 , wherein the open air gap filled with the electrically conductive material provide a fuse link.

10. A method of forming an electrical device comprising:
forming an air gap between at least one set of adjacent metal lines;
opening the air gaps;
forming a plurality of trench structures to a depth that does not communicate with the air gap; and
forming a conductive material within the trenches, wherein the conductive material deposited in the open air gap provides a vertical fuse, and the portion of the conductive material formed in the plurality of trench structures that do not communicate with the air gap provide interconnect structures.

11. The method of claim 10 , wherein forming said array of metal lines comprises:
depositing an intralevel dielectric layer on a substrate;
forming a plurality of line trenches in the intralevel dielectric layer; and
filling said plurality of line trenches with a metal to provide the array of metal lines.

12. The method of claim 11 , wherein forming said array of metal lines further comprise recessing the interlevel dielectric layer.

13. The method of claim 12 , wherein forming the air gap comprises:
depositing a dielectric cap atop and within the space separating adjacent metal lines within the array of metal lines.

14. The method of claim 13 , wherein a thickness of the dielectric cap pinches off within the space separating said adjacent metal lines to substantially enclose said air gap.

15. The method of claim 13 , wherein said forming the plurality of trenches in the interlevel dielectric layer comprises forming a first trench having a first depth portion and a second depth portion, wherein the second depth portion extends to said opened air gap, and forming a second trench having said first depth portion.

16. The method of claim 15 , wherein the second trench does not have a second depth portion.

17. The method of claim 16 , wherein the first depth portion provides a metal line.

18. The method of claim 17 , wherein the second depth portion provides vias.

19. The method of claim 18 , wherein said vias filled with the electrically conductive material provide a first contact region and a second contact region to the vertical fuse.

20. The method of claim 19 , wherein the open air gap filled with the electrically conductive material provide a fuse link.

Assignees

• IBM

Inventors

• Bergendahl Marc A
• Demarest James J
• Penny Christopher J
• Waskiewicz Christopher J

Classifications

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title