Open-loop correction of duty-cycle error and quadrature phase error

Patent metadata

Field	Value
Publication number	US-9444442-B2
Application number	US-201414165370-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Mar 6, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.

First claim

What is claimed is:

1. A method of for duty-cycle correction of a clock signal comprising:
receiving a clock signal in a clock-forwarded serial communication link;
sampling the received clock signal over a selected number of samples to measure a duty-cycle of the received clock signal;
estimating a delay to adjust the received clock signal to achieve a desired duty-cycle;
expressing the delay in terms of a phase code adjustment (Δ) compatible with a predetermined phase interpolator step size; and
conveying the phase code adjustment (Δ) to a transmitter to adjust the duty-cycle of the clock signal, using a phase interpolator, so as to achieve the desired duty-cycle of the received clock signal.

2. The method of claim 1 wherein the received clock signal comprises quadrature clock signals (ICLK and QCLK) and the method comprises applying the foregoing steps with regard to at least one of the quadrature clock signals.

3. The method of claim 2 wherein the desired duty-cycle is 50% for ICLK and 50% for QCLK so as to support quad data rate sampling of the serial communication link.

4. The method of claim 2 wherein the delay is applied to adjust a falling edge of at least one of the quadrature clock signals so as to maintain alignment of a rising edge of the at least one of the quadrature clock signals.

5. The method of claim 2 further comprising:
providing a second phase interpolator to generate a sampling clock signal to sample the received clock signal, wherein the second phase interpolator is characterized by the predetermined phase interpolator step size; and
sampling the received clock signal using the sampling clock signal generated by the second phase interpolator, to translate the delay to adjust the received clock signal into the phase code adjustment (Δ).

6. The method of claim 2 and further comprising conveying the phase code adjustment (Δ) to the transmitter in response to determining that the estimated delay exceeds a predetermined threshold value.

7. The method of claim 2 and further comprising conveying the phase code adjustment (Δ) to the transmitter after expiration of a predetermined time period since a last preceding adjustment.

8. The method of claim 2 and further comprising:
measuring a quadrature phase error (QPE) of the quadrature clock signals;
estimating a second delay to correct the quadrature phase error;
expressing the second delay in terms of a second phase code adjustment compatible with the predetermined phase interpolator step size; and
conveying the second phase code adjustment to the transmitter to correct the quadrature phase error.

9. The method of claim 8 wherein said measuring the quadrature phase error (QPE) comprises combining the quadrature clock signals to form a local clock signal (IQCLK), arranged so that a duty cycle of the local clock signal (IQCLK) is responsive to the quadrature phase error (QPE) of the quadrature clock signals.

10. The method of claim 9 wherein the local clock signal (IQCLK) exhibits a substantially linear relation to the quadrature phase error.

11. The method of claim 9 wherein a 90-degree phase difference between the quadrature clock signals generates approximately a 25% duty cycle of the local clock signal (IQCLK).

12. The method of claim 2 wherein the desired duty-cycle is within a range of 40% to 60% for ICLK and within a range of 40% to 60% for QCLK.

13. The method of claim 2 wherein sampling the received clock signal comprises:
providing a second phase interpolator;
generating multiple different sets of multi-phase clock signals, each set of multi-phase clock signals offset from the other sets;
inputting a first set of the multi-phase clock signals to the second phase interpolator to generate the sampling clock signal;
sampling the clock signal responsive to the first set of the multi-phase clock signals;
repeating said inputting and sampling steps so as to sample the clock signal utilizing at least one additional set of the multi-phase clock signals; and
combining the respective sample data acquired using multiple different sets of multi-phase clock signals so as to mitigate non-linearity effects of the phase interpolator.

14. The method of claim 13 wherein generating the different sets of multi-phase clock signals comprises:
dividing a first received clock signal by an integer divisor to form a first set of the multi-phase clock signals; and
dividing a quadrature received clock signal by the integer divisor to form a second set of the multi-phase clock signals.

15. A serial link transmitter comprising:
a clock circuit comprising a first phase interpolator (PI) arranged to generate a first clock signal, wherein the first PI is arranged to interpolate among multi-phase clock signals responsive to a first phase code input value;
a second PI arranged to interpolate among the multi-phase clock signals responsive to a second phase code input value to form a second clock signal; and
a correction circuit, operatively coupled to the clock circuit and the second PI, to combine the first and second clock signals to form a corrected clock signal.

16. The transmitter of claim 15 wherein the second phase code input value equals the first phase code input value offset by a delta received from a receiver of the serial link.

17. The transmitter of claim 16 wherein the delta is expressed directly in units of a step size of the first and second PIs.

18. The transmitter of claim 17 wherein the delta is selected at the receiver to achieve a 50% duty-cycle of the corrected clock signal as measured at the receiver.

19. A method of for estimating integral non-linearity (INL) comprising:
providing a source clock input signal to a phase interpolator (PI);
providing a selected phase code to the PI, the selected phase code associated with an expected duty cycle;
operating the PI to generate a delayed clock signal responsive to the source clock input signal and the selected phase code;
combining the source clock signal and the delayed clock signal to form a clock output signal;
measuring a duty cycle of the clock output signal;
comparing the measured duty cycle of the clock output signal to the expected duty cycle; and
estimating an integral non-linearity (INL) of the PI at the selected phase code, based on the said comparison.

20. The method of claim 19 and further comprising back calculating a delay of the PI for the selected phase code based on the said comparison of the measured duty cycle of the output clock signal to the expected duty cycle.

Assignees

• Rambus Inc

Inventors

• Chandrasekaran Srinivasaraman
• Srinivas Gundlapalli Shanmukha

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title