Digital-to-phase converter

Patent metadata

Field	Value
Publication number	US-9484900-B2
Application number	US-201414535744-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Nov 7, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.

First claim

What is claimed is:

1. A digital-to-phase converter circuit for producing a clock output having a digitally controlled phase, the circuit comprising:
a first pre-driver module configured to receive complementary in-phase clock signals and produce a first pair of complementary buffered clock signals having controlled slew rates;
a second pre-driver module configured to receive complementary quadrature clock signals and produce a second pair of complementary buffered clock signals having controlled slew rates; and
a mixer module configured to produce the clock output by forming a weighted combination of the buffered clock signals based on a phase control input, the mixer module comprising
a plurality of mixer cells, each of the plurality of mixer cells comprising four enableable inverters, each of the four enableable inverters having an input coupled to one of the buffered clock signals and an output coupled to a first mixer output, wherein one of the enableable inverters is enabled based on the phase control input; and
an output buffer configured to buffer the first mixer output to produce the clock output.

2. The circuit of claim 1 , wherein the controlled slew rates are controlled to produce full swings on the first pair of complementary buffered clock signals and the second pair of complementary buffered clock signals.

3. The circuit of claim 1 , wherein the first pre-driver module comprises:
a variable strength current source configured to control rising slew rates of the first pair of complementary buffered clock signals;
a variable strength current sink configured to control falling slew rates of the first pair of complementary buffered clock signals;
a first inverter coupled between the variable strength current source and the variable strength current sink and receiving one of the complementary in-phase clock signals and producing one of the first pair of complementary buffered clock signals; and
a second inverter coupled between the variable strength current source and the variable strength current sink and receiving the other one of the complementary in-phase clock signals and producing the other one of the first pair of complementary buffered clock signals.

4. The circuit of claim 1 , wherein each of the four enableable inverters includes:
a first p-channel transistor and a second p-channel transistor coupled in series between a voltage supply and the first mixer output, wherein the first p-channel transistor has a gate connected to the respective one of the buffered clock signals; and
a first n-channel transistor and a second n-channel transistor coupled in series between a ground reference and the first mixer output, wherein the first n-channel transistor has a gate connected to the respective one of the buffered clock signals.

5. The circuit of claim 1 , wherein the output buffer is further configured to correct for nonlinearities in a relationship between the phase of the first mixer output and the phase control input.

6. The circuit of claim 5 , wherein the output buffer comprises:
a variable strength source having a strength configured to correct for nonlinearities between the phase of the first mixer output and the phase control input;
a variable strength sink having a strength configured to correct for nonlinearities between the phase of the first mixer output and the phase control input;
a first inverter coupled between the variable strength source and the variable strength sink having an input coupled to the first mixer output and an output coupled to a first corrected output; and
a second inverter having an input coupled to the first corrected output and an output coupled to the clock output.

7. The circuit of claim 5 , wherein the output buffer configured to receive the first mixer output and produce complementary outputs, and wherein the output buffer comprises:
a variable strength source having a strength configured to correct for nonlinearities between the phase of the first mixer output and the phase control input;
a variable strength sink having a strength configured to correct for nonlinearities between the phase of the first mixer output and the phase control input;
a first inverter coupled between the variable strength source and the variable strength sink having an input coupled to a complement of the first mixer output and an output coupled to a first corrected output;
a second inverter coupled between the variable strength source and the variable strength sink having an input coupled to the first mixer output and an output coupled to a second corrected output;
a third inverter having an input coupled to the first corrected output and an output coupled to one of the complementary outputs; and
a fourth inverter having an input coupled to the second corrected output and an output coupled to the other one of the complementary outputs.

8. The circuit of claim 1 , further comprising a control module configured to control the slew rates of the first pre-driver module and the second pre-driver module based on one more of fabrication process conditions, supply voltage, temperature, and operating frequency.

9. The circuit of claim 1 , further comprising a second mixer module configured to produce a second clock output by forming a second weighted combination of the buffered clock signals based on the phase control input.

10. A method for producing a clock output having a digitally controlled phase, the method comprising:
buffering in-phase clock signals to produce a first pair of complementary buffered clock signals having controlled slew rates based on one or more of fabrication process conditions, supply voltage, temperature, and operating frequency;
buffering quadrature clock signals to produce a second pair of complementary buffered clock signals having controlled slew rates based on one or more of fabrication process conditions, supply voltage, temperature, and operating frequency; and
forming a weighted combination of the buffered clock signals to produce the clock output, wherein the weighted combination is selected to produce the digitally controlled phase.

11. The method of claim 10 , wherein the controlled slew rates are controlled to produce full swings on the first pair of complementary buffered clock signals and the second pair of complementary buffered clock signals.

12. The method of claim 10 , wherein buffing the in-phase clock signals to produce the first pair of complementary buffered clock signals utilizes a variable strength source to control rising slew rates of the first pair of complementary buffered clock signals and a variable strength sink to control falling slew rates of the first pair of complementary buffered clock signals.

13. The method of claim 10 , further comprising correcting for nonlinearities in a relationship between the phase of the clock output and the digitally controlled phase.

14. The method of claim 13 , wherein correcting for nonlinearities in the relationship between the phase of the clock output and the digitally controlled phase includes controlling a delay in buffer driving the clock output.

15. The method of claim 10 , further comprising forming a second weighted combination of the buffered clock signals to produce a second clock output.

16. An apparatus for producing a clock output having a digitally controlled phase, the apparatus including:
a means for driving a first pair of complementary buffered clock signals configured to receive complementary in-phase clock signals and produce the first pair of complementary buffered clock signals having controlled slew rates;
a means for driving a second pa

Assignees

• Qualcomm Inc

Inventors

• Cohen Hanan

Classifications

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title