Reference voltage generator and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10439632-B2
Application number	US-201816191367-A
Country	US
Kind code	B2
Filing date	Nov 14, 2018
Priority date	Nov 17, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

First claim

What is claimed is:

1. A semiconductor device comprising:
a reference voltage generator comprising a boosting code circuit and a first digital-analog converter (DAC), the reference voltage generator being configured to output a reference voltage,
wherein the boosting code circuit comprises a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse,
wherein the first DAC is configured to output the reference voltage by converting the first boosting code, and
wherein the first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

2. The semiconductor device of claim 1 , wherein the first DAC is configured to output the reference voltage having a first voltage level when the first boosting code has the first code value and output the reference voltage having a second voltage level less than the first voltage level when the first boosting code has the same value as the reference code.

3. The semiconductor device of claim 1 , wherein the first DAC is configured such that the first DAC is controlled in response to the first code value to target an output voltage that is twice as much as the reference voltage when the first boosting code has the same value as the reference code.

4. The semiconductor device of claim 1 , wherein the first boosting pulse generator is configured to determine a pulse width of the first boosting pulse based on the reference code.

5. The semiconductor device of claim 4 , wherein the first boosting pulse generator is configured such that the pulse width of the first boosting pulse at the first logic level increases as a target voltage level of the reference voltage corresponding to the reference code increases.

6. The semiconductor device of claim 1 , wherein the boosting code circuit further comprises a boosting voltage controller configured to output a second boosting code based on the reference code and the first boosting pulse, and
wherein the first DAC comprises an R- 2 R ladder DAC and a plurality of switches, each switch connecting each of a plurality of nodes of the first DAC and a power voltage to each other based on the second boosting code.

7. The semiconductor device of claim 1 , wherein the boosting code circuit further comprises a second boosting code controller configured to output a second boosting code based on the reference code and the first boosting pulse,
wherein the reference voltage generator further comprises a second DAC configured to output the reference voltage by converting the second boosting code, and
wherein the second boosting code has a second code value when the first boosting pulse has a first logic level, and has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

8. The semiconductor device of claim 7 , wherein the boosting code circuit further comprises a second pulse generator configured to generate an enable signal to enable a converting operation of the first DAC.

9. The semiconductor device of claim 1 , wherein the boosting code circuit further comprises a second boosting pulse generator configured to generate a second boosting pulse and a second boosting code controller configured to output a second boosting code based on the reference code and the second boosting pulse,
wherein the reference voltage generator further comprises a second DAC configured to output the reference voltage by converting the second boosting code, and
wherein the second boosting code has a second code value based on the reference code when the second boosting pulse has a first logic level, and has the same value as the reference code when the second boosting pulse has a second logic level opposite to the first logic level.

10. The semiconductor device of claim 9 , wherein a pulse width of the first boosting pulse at the first logic level is less than a pulse width of the second boosting pulse at the first logic level.

11. A semiconductor device comprising:
a reference voltage generator comprising a boosting code circuit and a first digital-analog converter (DAC), the reference voltage generator being configured to output a reference voltage,
wherein the boosting code circuit comprises a boosting pulse generator configured to generate a boosting pulse, and a boosting code controller configured to output a boosting code based on a reference code and the boosting pulse, and
wherein the first DAC is configured to output the reference voltage having a first voltage level by converting the boosting code having a different value from the reference code during a pulse duration of the boosting pulse, and output the reference voltage having a second voltage level less than the first voltage level by converting the boosting code having the same value as the reference code after the pulse duration of the boosting pulse when the boosting code circuit is activated.

12. The semiconductor device of claim 11 , wherein the first DAC comprises an R-2R ladder DAC and a plurality of first switches, each first switch connecting a first end of each resistor 2 R and a power voltage or a ground voltage to each other based on the boosting code.

13. The semiconductor device of claim 12 , wherein the boosting code circuit further comprises a boosting voltage controller configured to output a second boosting code based on the reference code and the boosting pulse,
wherein the first DAC comprises a plurality of second switches, each second switch connecting each node of a plurality of nodes of the first DAC and the power voltage to each other based on the second boosting code, and
wherein each node of the plurality of nodes of the first DAC is connected to a second end of each resistor 2 R.

14. The semiconductor device of claim 13 , wherein the boosting voltage controller is configured to connect at least one of the plurality of second switches to the power voltage during the pulse duration of the boosting pulse, and allows the plurality of second switches to open after the pulse duration of the boosting pulse.

15. The semiconductor device of claim 11 , wherein the first voltage level is twice of the second voltage level when the boosting code has a value that is twice as much as that of the reference code.

16. The semiconductor device of claim 11 , wherein the boosting pulse generator is configured to determine a pulse width of the boosting pulse based on the reference code.

17. The semiconductor device of claim 16 , wherein the boosting pulse generator is configured to generate the boosting pulse such that the pulse duration of the boosting pulse increases as a target voltage level of the reference voltage increases.

18. The semiconductor device of claim 11 , further comprising:
a second DAC configured to output the reference voltage on an output node connected to the first DAC by converting the reference code.

19. A semiconductor device comprising:
a reference voltage generator comprising a boosting code circuit and a digital-analog converter (DAC), the reference voltage generator being configured to output a reference voltage,
wherein the boosting code circuit includes a boosting code controller configured to output a boosting code based on a reference code, and

Assignees

• Samsung Electronics Co Ltd
• Samsing Electronics Co Ltd

Inventors

• Kavala Anil
• Lee Seon-Kyoo
• Jeong Byung-Hoon
• Ihm Jeong-Don
• Choi Young-Don

Classifications

• H03M1/0675

  using redundancy · CPC title

• H03M1/785 Primary

  using resistors, i.e. R-2R ladders · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G05F3/08 Primary

  wherein the variable is DC · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title