Driver and electronic device

US2016133218A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016133218-A1
Application numberUS-201514925319-A
CountryUS
Kind codeA1
Filing dateOct 28, 2015
Priority dateNov 7, 2014
Publication dateMay 12, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device having a driver that drives load lines in an electro-optical panel through capacitor charge redistribution is provided with a first driving capacitance circuit that drives the load lines, and a second driving capacitance circuit that drives output of a D/A conversion circuit for outputting a voltage corresponding to a driving voltage. Settling time of the output of the D/A conversion circuit is shortened by controlling the second driving capacitance circuit to set the output of the D/A conversion circuit to a desired output voltage.

First claim

Opening claim text (preview).

What is claimed is: 1 . A driver comprising: a voltage driving circuit that amplifies a voltage of an input node and outputs the amplified voltage as a data voltage to a data voltage output terminal; a D/A conversion circuit that selects a reference voltage corresponding to tone data from among a plurality of reference voltages, and outputs the selected reference voltage to the input node of the voltage driving circuit; an auxiliary capacitor driving circuit that outputs first to nth auxiliary capacitor driving voltages (n is a natural number of 2 or more) corresponding to the tone data to first to nth auxiliary capacitor driving nodes; and an auxiliary capacitor circuit having first to nth auxiliary capacitors provided between the input node of the voltage driving circuit and the first to nth auxiliary capacitor driving nodes. 2 . The driver according to claim 1 , further comprising: a capacitor driving circuit that outputs first to nth capacitor driving voltages corresponding to the tone data to first to nth capacitor driving nodes; and a capacitor circuit having first to nth capacitors provided between the first to nth capacitor driving nodes and the data voltage output terminal, wherein after capacitive driving for driving an electro-optical panel is started by the capacitor driving circuit and the capacitor circuit, the voltage driving circuit carries out voltage driving for outputting the data voltage to the data voltage output terminal. 3 . The driver according to claim 2 , wherein a capacitance of an ith auxiliary capacitor (i is a natural number no greater than n) in the first to nth auxiliary capacitors is smaller than a capacitance of an ith capacitor in the first to nth capacitors. 4 . The driver according to claim 1 , wherein the auxiliary capacitor circuit has a switching circuit provided between the input node of the voltage driving circuit and the first to nth auxiliary capacitors. 5 . The driver according to claim 4 , wherein the switching circuit turns off from an on state before the voltage driving circuit starts voltage driving for outputting the data voltage to the data voltage output terminal. 6 . The driver according to claim 5 , wherein the voltage driving circuit includes: an amplifier circuit that outputs the data voltage; and a voltage driving switching circuit provided between output of the amplifier circuit and the data voltage output terminal, wherein the switching circuit of the auxiliary capacitor circuit turns off from an on state before the voltage driving switching circuit turns on from an off state. 7 . The driver according to claim 1 , wherein the voltage driving circuit is an inverting amplifier circuit. 8 . The driver according to claim 7 , wherein the auxiliary capacitor driving circuit outputs the first to nth auxiliary capacitor driving voltages corresponding to logically inverted data of the tone data. 9 . The driver according to claim 2 , further comprising: a variable capacitance circuit provided between the data voltage output terminal and a reference voltage node, wherein a capacitance of the variable capacitance circuit is set so that a capacitance obtained by adding the capacitance of the variable capacitance circuit and an electro-optical panel-side capacitance is in a prescribed capacitance ratio relationship with a capacitance of the capacitor circuit. 10 . An electronic device comprising the driver according to claim 1 . 11 . An electronic device comprising the driver according to claim 2 . 12 . An electronic device comprising the driver according to claim 3 . 13 . An electronic device comprising the driver according to claim 4 . 14 . An electronic device comprising the driver according to claim 5 . 15 . An electronic device comprising the driver according to claim 6 . 16 . An electronic device comprising the driver according to claim 7 . 17 . An electronic device comprising the driver according to claim 8 . 18 . An electronic device comprising the driver according to claim 9 .

Assignees

Inventors

Classifications

  • G09G3/3696Primary

    Generation of voltages supplied to electrode drivers · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

  • Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

  • Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

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What does patent US2016133218A1 cover?
A display device having a driver that drives load lines in an electro-optical panel through capacitor charge redistribution is provided with a first driving capacitance circuit that drives the load lines, and a second driving capacitance circuit that drives output of a D/A conversion circuit for outputting a voltage corresponding to a driving voltage. Settling time of the output of the D/A conv…
Who is the assignee on this patent?
Seiko Epson Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/3696. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).