Apparatus for digital-to-analog conversion with improved performance and associated methods

Patent metadata

Field	Value
Publication number	US-2016359497-A1
Application number	US-201514732700-A
Country	US
Kind code	A1
Filing date	Jun 6, 2015
Priority date	Jun 6, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.

First claim

1 . An apparatus comprising:
a digital-to-analog converter (DAC) to convert a digital input signal to an analog output signal, the DAC comprising:
a decoder to decode the digital input signal and to provide first and second sets of control signals;
a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals; and
an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.

2 . The apparatus according to claim 1 , wherein the DAC provides the analog output signal with monotonicity.

3 . The apparatus according to claim 1 , wherein the RDAC comprises a resistor network coupled to a first switch network, the first switch network comprising a first set of switches controlled by the first set of control signals.

4 . The apparatus according to claim 3 , wherein the first set of control signals are generated by the decoder by decoding more-significant bits (MSB) of the digital input signal.

5 . The apparatus according to claim 4 , wherein the decoder comprises a binary decoder to decode the MSB of the digital input signal to generate the first set of control signals.

6 . The apparatus according to claim 1 , wherein the interpolator comprises a second switch network coupled to a plurality of interpolator stages, the second switch network comprising a second set of switches controlled by the second set of control signals.

7 . The apparatus according to claim 6 , wherein the second set of control signals are generated by the decoder by decoding less-significant bits (LSB) of the digital input signal.

8 . The apparatus according to claim 7 , wherein the decoder comprises a thermometer decoder to decode the LSB of the digital input signal to generate the first set of control signals.

9 . The apparatus according to claim 6 , further comprising an output stage coupled to the interpolator to receive the first analog signal and to provide the analog output signal.

10 . An apparatus comprising:
a digital-to-analog converter (DAC) comprising:
a current-source network comprising a plurality of current sources to provide a plurality of currents;
a first switch network to selectively provide the plurality of currents provided by the plurality of current sources to a first node or a second node;
a resistor network coupled to provide an output signal, the resistor network comprising a plurality of resistors; and
a second switch network coupled to the resistor network to selectively couple resistors in the plurality of resistors of the resistor network to the first and second nodes.

11 . The apparatus according to claim 10 , wherein the DAC provides the output signal with monotonicity.

12 . The apparatus according to claim 10 , wherein the first switch network comprises a plurality of pairs of switches coupled to respective current sources in the current-source network to selectively provide to the first node or the second the currents provided by the plurality of current sources.

13 . The apparatus according to claim 10 , wherein the first switch network comprises a pair of switches coupled to receive a current from a current source in the current-source network, the current flowing evenly in the pair of switches in order to increase a resolution of the DAC.

14 . The apparatus according to claim 10 , wherein the resistor network is coupled between an output of the DAC and a ground node of the DAC.

15 . A method of converting a digital signal to an analog signal, the method comprising:
decoding the digital signal to generate a first set of control signals and a second set of control signals; providing, by using a resistor DAC (RDAC), first and second voltages in response to the first set of control signals; and interpolating the first and second voltages to provide a first analog signal in response to the second set of control signals.

16 . The method according to claim 15 , wherein converting a digital signal to an analog signal is performed with monotonicity.

17 . The method according to claim 15 , wherein using the RDAC to provide the first and second voltages comprises, in response to the first set of control signals, selectively coupling resistors in a resistor network to nodes having the first and second voltages.

18 . The method according to claim 17 , wherein decoding the digital signal further comprises decoding more-significant bits (MSB) of the digital signal to generate the first set of control signals.

19 . The method according to claim 15 , wherein interpolating the first and second voltages comprises, in response to the second set of control signals, selectively providing the first and second voltages to a plurality of interpolator stages.

20 . The method according to claim 19 , wherein decoding the digital signal further comprises decoding less-significant bits (LSB) of the digital signal to generate the second set of control signals.

Assignees

• Silicon Lab Inc

Inventors

• Thomsen Axel
• Westwick Alan L

Classifications

• H03M1/0609 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/664

  Non-linear conversion not otherwise provided for in subgroups of H03M1/66 · CPC title

• H03M1/682

  both converters being of the unary decoded type · CPC title

• H03M1/808

  using resistors · CPC title