Switch circuit, analog-to-digital converter, and integrated circuit

Patent metadata

Field	Value
Publication number	US-9444483-B2
Application number	US-201514757547-A
Country	US
Kind code	B2
Filing date	Dec 24, 2015
Priority date	Jan 29, 2015
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

First claim

What is claimed is:

1. A switch circuit comprising:
a sampling transistor including a source connected to an input node and a drain connected to an output node;
a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor;
a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and
a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

2. The switch circuit according to claim 1 , wherein
the voltage holding circuit includes:
a power storage capacitance element;
a first charge switch configured to connect one terminal of the power storage capacitance element to a first potential power source;
a second charge switch configured to connect the other terminal of the power storage capacitance element to a second potential power source whose voltage is lower than a voltage of the first potential power source;
an input connection switch which is connected between the input node and the other terminal of the power storage capacitance element; and
a gate connection switch which is connected between the gate of the sampling transistor and the one terminal of the power storage capacitance element,

wherein
when the sampling transistor turns on, the input connection switch and the gate connection switch turn on, the first charge switch and the second charge switch turn off, and the power storage capacitance element supplies a first voltage to the gate of the sampling transistor, the first voltage being obtained by adding the voltage of the power storage capacitance element to the voltage of the input node, and
when the sampling transistor turns off, the input connection switch and the gate connection switch turn off, the first charge switch and the second charge switch turn on, and the power storage capacitance element is charged.

3. The switch circuit according to claim 2 , wherein
the control circuit includes a first transistor and a second transistor which are connected in series between the gate of the sampling transistor and the second potential power source,
the first transistor and the second transistor turn on when the sampling transistor turns off, and
at least one of the first transistor and the second transistor turns off when the sampling transistor turns on.

4. The switch circuit according to claim 2 , wherein
the protection circuit includes:
a first damping capacitance element and a second damping capacitance element which are connected in series between the gate of the sampling transistor and the second potential power source; and
a damping switch which is connected between a connection node of the first damping capacitance element and the second damping capacitance element, and the second potential power source, wherein

the damping switch enters a conduction state when the sampling transistor is turned off and enters a cutoff state when the sampling transistor is turned on, and
the damping switch enters the conduction state before the gate connection switch is cut off and the first transistor and the second transistor are brought into conduction when the sampling transistor makes a transition from on to off.

5. The switch circuit according to claim 3 , wherein
the protection circuit includes:
a first damping capacitance element and a second damping capacitance element which are connected in series between the gate of the sampling transistor and the second potential power source; and
a damping switch which is connected between a connection node of the first damping capacitance element and the second damping capacitance element, and the second potential power source, wherein

the damping switch enters a conduction state when the sampling transistor is turned off and enters a cutoff state when the sampling transistor is turned on, and
the damping switch enters the conduction state before the gate connection switch is cut off and the first transistor and the second transistor are brought into conduction when the sampling transistor makes a transition from on to off.

6. An analog-to-digital converter comprising:
a sampling circuit configured to sample an analog signal; and
an AD conversion unit configured to convert the analog signal into a digital signal, wherein
the sampling circuit includes:
a sampling capacitance element; and
a switch circuit configured to control turning on or off of inputting of the analog signal to the sampling capacitance element, wherein and

the switch circuit includes:
a sampling transistor including a source connected to an input node and a drain connected to an output node;
a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor;
a voltage holding circuit which is provided between the gate and the source of the sampling transistor and which maintains a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and
a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.

7. The analog-to-digital converter according to claim 6 , wherein
the voltage holding circuit includes:
a power storage capacitance element;
a first charge switch configured to connect one terminal of the power storage capacitance element to a first potential power source;
a second charge switch configured to connect the other terminal of the power storage capacitance element to a second potential power source whose voltage is lower than a voltage of the first potential power source;
an input connection switch which is connected between the input node and the other terminal of the power storage capacitance element; and
a gate connection switch which is connected between the gate of the sampling transistor and the one terminal of the power storage capacitance element,

wherein
when the sampling transistor turns on, the input connection switch and the gate connection switch turn on, the first charge switch and the second charge switch turn off, and the power storage capacitance element supplies a first voltage to the gate of the sampling transistor, the first voltage being obtained by adding the voltage of the power storage capacitance element to the voltage of the input node, and
when the sampling transistor turns off, the input connection switch and the gate connection switch turn off, the first charge switch and the second charge switch turn on, and the power storage capacitance element is charged.

8. The analog-to-digital converter according to claim 7 , wherein
the control circuit includes a first transistor and a second transistor which are connected in series between the gate of the sampling transistor and the second potential power source,
the first transistor and the second transistor turn on when the sampling transistor turns off, and
at least one of the first transistor and the second transistor turns off when the sampling transistor turns on.

9. The analog-to-digital converter according to claim 7 , wherein
the protection circuit includes:
a first damping capacitance element and a second damping capacitance element which are connected in series between the gate of the sampling transistor and t

Assignees

• Socionext Inc

Inventors

• Okamoto Seiji

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• G11C27/02 Primary

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• H03K17/08122 Primary

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title