Methods of manufacturing electronic devices formed in a cavity

Patent metadata

Field	Value
Publication number	US-10439587-B2
Application number	US-201715828625-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Dec 2, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

Methods of manufacturing an electronic device formed in a cavity may include providing a first substrate having a first side wall including a first metal formed along a periphery on a bottom surface thereof and surrounding an electronic circuit disposed on the bottom surface, providing a second substrate having a second side wall including a second metal and a third metal formed along a periphery on a top surface thereof, aligning the first substrate with the second substrate with the first side wall opposing and contacting the second side wall to internally define a cavity between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall ,and the second side wall, and heating and bonding the first substrate and the second substrate by transient liquid phase bonding.

First claim

What is claimed is:

1. A method of manufacturing an electronic device, the method comprising:
providing a first substrate having a first side wall formed along a periphery of a bottom surface of the first substrate, the first side wall surrounding an electronic circuit disposed on the bottom surface of the first substrate, the first side wall being formed of a first metal layer made of a first metal;
providing a second substrate having a second side wall formed along a periphery of a top surface of the second substrate, the second side wall being formed of a second metal layer made of a second metal and a third metal layer made of a third metal sequentially stacked, the second metal and the third metal being different from each other and from the first metal;
aligning the first substrate with the second substrate to internally define a cavity between the bottom surface of the first substrate, the top surface of the second substrate, the first side wall, and the second side wall, the first side wall opposing and contacting the second side wall; and
heating the first substrate and the second substrate to bond the first side wall and the second side wall with each other by transient liquid phase bonding, the third metal layer being melted to form a first alloy layer and a second alloy layer with the first metal layer and the second metal layer respectively.

2. The method of claim 1 wherein providing the first substrate includes providing a substrate having a piezoelectric body, the electronic circuit including at least one of a film bulk acoustic resonator, a bulk acoustic wave element, a solidly mounted resonator, and a surface acoustic wave element.

3. The method of claim 1 wherein the third metal has a melting point lower than that of the second metal.

4. The method of claim 1 wherein the third metal layer is eliminated when the first alloy layer and the second alloy layer are formed.

5. The method of claim 1 further comprising forming the second side wall with a height greater than a height of the first side wall.

6. The method of claim 1 further comprising forming the second side wall with a width greater than a width of the first side wall.

7. The method of claim 1 wherein a starting temperature of alloy forming between the third metal layer and the second metal layer is lower than a starting temperature of alloy forming between the third metal layer and the first metal layer.

8. The method of claim 7 wherein there is no state where the first metal, the second metal, and the third metal are each concurrently melted during the transient liquid phase bonding.

9. The method of claim 1 wherein the first metal includes gold.

10. The method of claim 9 wherein the second metal includes copper.

11. The method of claim 9 wherein the third metal includes at least one of tin and indium.

12. The method of claim 1 wherein the first substrate has a thickness different from that of the second substrate.

13. The method of claim 1 further comprising forming a column between the bottom surface of the first substrate and the top surface of the second substrate within the cavity.

14. The method of 13 wherein forming the column comprises forming the column from a layer of the first alloy stacked on a layer of the second alloy.

15. The method of claim 14 wherein forming the column comprises forming the column with the layer of the first alloy being tapered.

16. The method of claim 1 further comprising forming a via through the first substrate, side surfaces of the via having a surface roughness greater than a surface roughness of the bottom surface of the first substrate.

17. The method of claim 16 wherein forming the via includes forming a first stop layer including a first metal on the bottom surface of the first substrate, forming a second stop layer including a second metal on the first stop layer, and etching the first substrate to form the via, etching of the first substrate terminating on one of the first stop layer and the second stop layer.

18. The method of claim 16 further comprising forming an external electrode including a first material layer having a portion passing through the via and an upwardly extending portion extending above an upper surface of the first substrate.

19. The method of claim 16 further comprising forming an electrical connection between the via and the electronic circuit.

20. The method of claims 16 further comprising forming a column coupled to the via and to the top surface of the second substrate.

21. The method of claim 1 wherein providing the first substrate includes providing the first substrate with a surface roughness of an upper surface of the first substrate greater than a surface roughness of the bottom surface of the first substrate.

22. The method of claim 1 wherein forming the first alloy layer comprises forming the first alloy layer with a tapered cross section.

23. The method of claim 1 further comprising bonding the first substrate and the second substrate to a top surface of a printed circuit board and covering the top surface of the printed circuit board with resin including a filler having particles with an average diameter, the first side wall and the second side wall being internally withdrawn from respective peripheries of the first substrate and the second substrate by a distance that is half or less of the average diameter of the particles of the filler.

Assignees

• Skyworks Solutions Inc

Inventors

• Takano Atsushi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/072

  of bump connectors · CPC title