Bad bit register for memory

Patent metadata

Field	Value
Publication number	US-10437665-B2
Application number	US-201715842692-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Jun 22, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

First claim

What is claimed is:

1. A memory device, comprising:
a non-volatile random access memory, including:
a suspect bit register configured to store addresses of bits that are determined to have had errors; and
a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error.

2. The memory device of claim 1 , wherein the suspect bit register is configured to store the addresses of the bits that are determined to have had the errors occurring subsequent to a burn-in process, and the memory device further comprises a main register configured to identify bits determined to have errors during a burn-in process.

3. The memory device of claim 2 , wherein the main register and the bad bit register are configured as a fuse bit register.

4. The memory device of claim 3 , wherein the main register and the bad bit register are comprised in the non-volatile random access memory.

5. The memory device of claim 2 , wherein the bits determined to be bad during the burn-in process correspond to electrical short circuit conditions and electrical open circuit conditions.

6. The memory device of claim 2 , wherein the main register is included in the non-volatile random access memory.

7. The memory device of claim 2 , wherein the main register is included in a one-time-programmable memory device.

8. The memory device of claim 1 , wherein the non-volatile random access memory is a Spin Torque Magnetoresistive Random Access Memory having magnetic tunnel junctions.

9. The memory device of claim 1 , wherein an oldest one of addresses in the suspect bit register is written over, responsive to the suspect bit register being full and an address being pending for writing to the suspect bit register.

10. The memory device of claim 1 , wherein an oldest one of the addresses in the bad bit register is written over, responsive to the bad bit register being fill and an address being pending for writing to the bad bit register.

11. A memory system, comprising:
a bad bit register configured to store addresses of words that include bits determined to have an unacceptable write-error rate;
a suspect bit register configured to identify bad bits to write into the bad bit register;
a processor, configured to:
search for an address of a bit relating to the error in the suspect bit register, responsive to detecting an error using an error correction code, and
remove the address of the bit relating to the error from the suspect bit register and write the address of the bit relating to the error into the bad bit register, responsive to a presence of the match.

12. The memory system of claim 11 , wherein the processor is configured to write the address of the bit relating to the error into the suspect bit register, responsive to an absence of the match.

13. The memory system of claim 11 , further comprising a main register configured to identify bits determined to be bad during a burn-in process.

14. The memory system of claim 13 , wherein the main register and the bad bit register are configured as a fuse bit register, and wherein the processor is configured to use the fuse bit register to fuse out words determined to be bad and replace each of the words determined to be bad with a respective redundant address.

15. The memory system of claim 11 , wherein the bad bit register, the suspect bit register, and the main register are comprised in a same non-volatile memory device.

16. The memory system of claim 11 , wherein the bad bit register and the suspect bit register are comprised in a same non-volatile memory device, and the main register is comprised in a different non-volatile memory device.

Assignees

• IBM

Inventors

• Debrosse John K
• Worledge Daniel C

Classifications

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C2029/0403

  during or with feedback to manufacture · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/4401 Primary

  for self repair · CPC title