Voltage-controlled magnetic memory element with canted magnetization

Patent metadata

Field	Value
Publication number	US-9036407-B2
Application number	US-201314101260-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Dec 7, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A memory cell including information that is stored in the state of a magnetic bit (i.e. in a free layer, FL), where the FL magnetization has two stable states that may be canted (form an angle) with respect to the horizontal and vertical directions of the device is presented. The FL magnetization may be switched between the two canted states by the application of a voltage (i.e. electric field), which modifies the perpendicular magnetic anisotropy of the free layer.

First claim

What is claimed is:

1. A memory element, comprising:
a ferromagnetic free layer; and
a ferromagnetic fixed layer separated from the free layer;
wherein information is stored in a magnetization state of the free layer;
wherein said magnetization state comprises two stable states that are canted to form an angle with respect to horizontal and vertical directions of the free layer; and
wherein the free layer magnetization is switchable between the two canted states by the application of a voltage to modify the perpendicular magnetic anisotropy of the free layer.

2. A memory element as recited in claim 1 , wherein the free layer and fixed layer are separated by a dielectric layer.

3. A memory element as recited in claim 2 , wherein the dielectric layer comprises a metal oxide.

4. A memory element as recited in claim 2 , wherein the fixed layer has a magnetization orientation that is in-plane with respect to the fixed layer and free layer.

5. A memory element as recited in claim 2 , wherein the fixed layer has a magnetization orientation that is out-of-plane with respect to the fixed layer and free layer.

6. A memory element as recited in claim 2 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by a magnitude of a voltage applied across the fixed layer and free layer.

7. A memory element as recited in claim 2 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by a width of a voltage pulse applied across the fixed layer and free layer.

8. A memory element as recited in claim 2 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by setting the magnetization into a precessional motion upon application of a voltage pulse having a pulse width timed to affect switching to an opposite stable canted state.

9. A memory element as recited in claim 2 , wherein the free layer comprises an energy barrier configured such that the direction of switching between the two canted states is affected by setting the magnetization into a semi-stable state upon application of a voltage and then achieving switching through thermal activation.

10. A memory element as recited in claim 2 , wherein the canted free layer magnetization states comprise a stable high resistance state HR and low resistance state LR.

11. A memory element as recited in claim 2 , wherein the dielectric Layer comprises a tunneling barrier having a thickness large enough to substantially negate current-induced spin-transfer-torque (STT).

12. A memory element as recited in claim 2 , wherein the free layer has a thickness configured to correspond to a compensation point between in-plane shape anisotropy and interfacial perpendicular anisotropy to allow for maximized tunability of the free layer magnetization by application of voltage.

13. A memory element as configured in claim 2 , wherein free layer, fixed layer, and dielectric layer are disposed within a cell forming magneto-electric random access memory (MERAM).

14. A memory element as configured in claim 2 , further comprising a second fixed layer separated from the free layer by a metal spacer.

15. A memory element as configured in claim 14 :
wherein the fixed layer has a magnetization orientation that is in-plane with respect to the fixed layer and free layer; and
wherein the second fixed layer has a magnetization orientation that is out-of-plane with respect to the fixed layer and free layer.

16. A memory element as recited in claim 14 :
wherein the fixed layer has a magnetization orientation that is out-of-plane with respect to the fixed layer and free layer; and
wherein the second fixed layer has a magnetization orientation that is in-plane with respect to the fixed layer and free layer.

17. A magnetic tunnel junction, comprising:
a ferromagnetic free layer having a magnetization state; and
a ferromagnetic fixed layer separated from the free layer by a dielectric layer;
wherein said magnetization state comprises two stable states that are canted to form an angle with respect to horizontal and vertical directions of the free layer; and
wherein the free layer magnetization is switchable between the two canted states by the application of a voltage that modifies the perpendicular magnetic anisotropy of the free layer.

18. A magnetic tunnel junction as recited in claim 17 , wherein information is stored in a magnetization state of the free layer to form a memory cell.

19. A magnetic tunnel junction as recited in claim 17 , wherein the fixed layer has a magnetization orientation that is in-plane with respect to the fixed layer and free layer.

20. A magnetic tunnel junction as recited in claim 17 , wherein the fixed layer has a magnetization orientation that is out-of-plane with respect to the fixed layer and free layer.

21. A magnetic tunnel junction as recited in claim 17 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by a magnitude of a voltage applied across the fixed layer and free layer.

22. A magnetic tunnel junction as recited in claim 17 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by a width of a voltage pulse applied across the fixed layer and free layer.

23. A magnetic tunnel junction as recited in claim 17 , wherein the free layer, fixed layer, and dielectric layer are configured such that the direction of switching between the two canted states is affected by setting the magnetization into a precessional motion upon application of a voltage pulse having a pulse width timed to affect switching to an opposite stable canted state.

24. A magnetic tunnel junction as recited in claim 17 , wherein the free layer comprises an energy barrier configured such that the direction of switching between the two canted states is affected by setting the magnetization into a semi-stable state upon application of a voltage and then achieving switching through thermal activation.

25. A magnetic tunnel junction as recited in claim 17 , wherein the canted free layer magnetization states comprise a stable high resistance state HR and low resistance state LR.

26. A magnetic tunnel junction as recited in claim 17 , wherein the dielectric barrier comprises a tunneling barrier having a thickness large enough to substantially negate current-induced spin-transfer-torque (STT).

27. A magnetic tunnel junction as recited in claim 17 , wherein the free layer has a thickness configured to correspond to a compensation point between in-plane shape anisotropy and interfacial perpendicular anisotropy to allow for maximized tunability of the free layer magnetization by application of voltage.

28. A method for storing memory within a memory cell, comprising:
applying a voltage across a ferromagnetic free layer and a ferromagnetic fixed layer separated from the free layer by a dielectric layer;
wherein the free layer comprises a magnetization state; and
wherein said magnetization state comprises two stable states that are canted to form an angle with respect to horiz

Assignees

• Univ California

Inventors

• Wang Kang L
• Khalili Amiri Pedram
• Alzate Juan G

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H10N50/85 Primary

  Materials of the active region · CPC title

• H01L43/10 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic