Shielded magnetoresistive random access memory devices and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-10431732-B2
Application number	US-201715609621-A
Country	US
Kind code	B2
Filing date	May 31, 2017
Priority date	May 31, 2017
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

First claim

What is claimed is:

1. A magnetically shielded semiconductor device comprising:
a substrate having a top surface and a bottom surface;
an electromagnetic-field-susceptible semiconductor component located in the substrate;
a top magnetic shield located over the top surface of the substrate, wherein the top magnetic shield is formed with an opening;
a package substrate mounted to the top magnetic shield, wherein the package substrate defines a void vertically aligned with the opening of the top magnetic shield such that the package substrate lies free from directly disposing over the opening of the top magnetic shield;
a bottom magnetic shield located under the bottom surface of the substrate; and
a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

2. The magnetically shielded semiconductor device of claim 1 wherein the electromagnetic-field-susceptible semiconductor component includes a ferromagnetic memory cell.

3. The magnetically shielded semiconductor device of claim 1 wherein the electromagnetic-field-susceptible semiconductor component includes a magnetoresistive random access memory (MRAM) component.

4. The magnetically shielded semiconductor device of claim 1 wherein the sidewall magnetic shield is integral with the bottom magnetic shield, and wherein magnetic epoxy interconnects the sidewall magnetic shield and the top magnetic shield.

5. The magnetically shielded semiconductor device of claim 1 wherein a layer of magnetic epoxy interconnects the bottom surface of the substrate and the bottom magnetic shield.

6. The magnetically shielded semiconductor device of claim 1 wherein a layer of magnetic epoxy interconnects the top surface of the substrate and the top magnetic shield.

7. The magnetically shielded semiconductor device of claim 1 wherein:
the substrate has a first edge distanced from a second edge by a chip length;
the top magnetic shield has a first end distanced from a second end by a first length greater than the chip length;
the bottom magnetic shield has a first end distanced from a second end by a second length greater than the chip length;
a first portion of the sidewall magnetic shield has an inner surface distanced from the first edge by a first gap; and
a second portion of the sidewall magnetic shield has an inner surface distanced from the second edge by a second gap.

8. The magnetically shielded semiconductor device of claim 1 wherein the magnetically shielded semiconductor device further comprises wire connections coupled to the semiconductor component and to an upper surface of the package substrate, wherein the wire connections extend from the top surface, through the opening in the top magnetic shield, and through the void in the package substrate.

9. The magnetically shielded semiconductor device of claim 8 wherein the top magnetic shield is mounted to the package substrate.

10. The magnetically shielded semiconductor device of claim 1 wherein the electromagnetic-field-susceptible semiconductor component includes a magnetic tunnel junction (MTJ) array, and wherein the magnetically shielded semiconductor device further comprises wire connections coupled to the semiconductor component and to an upper surface of the package substrate, wherein the wire connections extend through the opening in the top magnetic shield and through the void in the package substrate.

11. A magnetically shielded semiconductor device comprising:
a cup-shaped magnetic shield defining a hollow;
a magnetoresistive random access memory (MRAM) die located at least partially within the hollow of the cup-shaped magnetic shield;
a second magnetic shield located over the MRAM die, wherein the second magnetic shield is formed with an annular slot opening completely removing a central portion of the second magnetic shield from an outer annular portion of the second magnetic shield; and
a package substrate mounted on the second magnetic shield, wherein the package substrate defines an opening vertically aligned with the annular slot opening of the second magnetic shield.

12. The magnetically shielded semiconductor device of claim 11 wherein magnetic epoxy interconnects the cup-shaped magnetic shield and the second magnetic shield.

13. The magnetically shielded semiconductor device of claim 11 wherein the cup-shaped magnetic shield has a recess surface, and wherein the magnetically shielded semiconductor device further comprises a layer of magnetic epoxy interconnecting the MRAM die and the recess surface.

14. The magnetically shielded semiconductor device of claim 11 wherein the magnetically shielded semiconductor device further comprises a layer of magnetic epoxy interconnecting the MRAM die and the second magnetic shield.

15. The magnetically shielded semiconductor device of claim 11 wherein:
the MRAM die has a first edge distanced from a second edge by a chip length;
the second magnetic shield has a first end distanced from a second end by a first length greater than the chip length;
the cup-shaped magnetic shield has a first end distanced from a second end by a second length greater than the chip length;
the cup-shaped magnetic shield has a first inner sidewall surface distanced from the first edge by a first gap; and
the cup-shaped magnetic shield has a second inner sidewall surface distanced from the second edge by a second gap.

16. The magnetically shielded semiconductor device of claim 11 wherein the magnetically shielded semiconductor device further comprises wire connections coupled to the MRAM die and extending from the MRAM die and through the annular slot opening in the second magnetic shield.

17. The magnetically shielded semiconductor device of claim 11 further comprising:
a package substrate, wherein the second magnetic shield is mounted to the package substrate and wherein the package substrate defines an opening aligned with the annular slot opening in the second magnetic shield; and
wire connections coupled to the MRAM die and to the package substrate, wherein the wire connections extend from the MRAM die and through the annular slot opening to the package substrate.

18. The magnetically shielded semiconductor device of claim 11 wherein the MRAM die includes a magnetic tunnel junction (MTJ) array, and wherein the magnetically shielded semiconductor device further comprises:
a package substrate, wherein the second magnetic shield is mounted to the package substrate, and wherein the package substrate defines an opening aligned with the annular slot opening in the second magnetic shield; and
wire connections coupled to the MRAM die and to the package substrate, wherein the wire connections extend from the MRAM die and through the annular slot opening to the package substrate.

19. A magnetically shielded semiconductor device comprising:
a cup-shaped magnetic shield defining a hollow;
an array of magnetic tunnel junction (MTJ) cells located in a magnetoresistive random access memory (MRAM) die, wherein the MRAM die is located at least partially within the hollow of the cup-shaped magnetic shield;
a second magnetic shield having an opening located over the MRAM die;
a package substrate mounted to the second magnetic shield and having an upper surface, wherein the package substrate defines an opening vertically aligned with the opening of the second magnetic shield; and
wire connections coupled to the MRAM die and to the upper surface of the package substrate, wherein the wire connections are free from disposing between the package subst

Assignees

• Globalfoundries Sg Pte Ltd
• Inst Of Microelectronics
• Agency Science Tech & Res

Inventors

• Bharat Bhushan
• Gao Shan
• Shum Danny Pak-Chum
• Yi Wanbing
• Tan Juan Boon
• Lim Wei Yi
• Lim Teck Guan
• Kwong Michael Han Kim
• Ching Eva Wai Leong

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title