Precision data access using differential data

Patent metadata

Field	Value
Publication number	US-10430326-B2
Application number	US-201615385960-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 15, 2014
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

First claim

What is claimed is:

1. A memory controller for storing and reading data elements to and from a memory, the memory controller comprising:
a storage unit configured to store a data element as a base word in a first precision and for storing one or more delta words comprising additional information related to a second precision version of the stored data element,

wherein:
the data element and each of the one or more delta words is stored in a separate memory bank, and
the separate memory banks facilitate the one or more delta words to be read with the base word from the separate memory banks during a single processor cycle; and

the memory controller further comprising an access unit configured to read:
the base word and the one or more delta words of the stored data element to access the data element in the second precision; and
a second base word and a second set of one or more delta words of a second stored data element;

wherein:
the reading of the base word and delta words of the stored data element and the second stored data element occurs during a single processor cycle;
the storage unit is further configured to store one or more delta words comprising additional information related to a third precision version of the stored data element;
the second precision is higher than the first precision and the third precision is higher than the second precision;
the access unit is further configured to read the base word, the one or more delta words comprising additional information related to the second precision, and the one or more delta words comprising additional information related to the third precision to access the data element in the third precision;
each of the base word and the delta words are a width of a central processing unit register of a computer system;
the base word and each delta word are stored in different memory banks and read in parallel from the different memory banks;
a precision select signal that is usable to address the different memory banks;
the base word is a signed data word containing a sign bit;
accessing the data element in the third precision comprises adding, by a shuffling unit of a memory controller, a first set of the delta words between the sign bit and the remaining bits of the base word and adding a second set of the delta words as least significant bits;
the shuffling unit of the memory controller is further configured to split the data element into the base word and a specified precision;
the reading of the base word and the one or more delta words of the stored data element, and the second base word and the second one or more delta words of the second stored data element comprises utilizing an addressing data element;
the access unit comprises:
a first set of address components connected to a least significant bit (LSB) of a bank select signal, the first set of address components comprising a first inverter and a first set of MUXes; and
a second set of address components connected to a most significant bit (MSB) of the bank select signal, the second set of address components comprising a second inverter and a second set of MUXes;

the memory controller is further configured to apply:
the precision select signal to a first MUX of the first set of MUXes;
the LSB of the bank select signal to each of the first set of MUXes and to an input of the first inverter, wherein an output of the first inverter is applied to a first subset that does not include the first MUX of the first set of MUXes;
the precision select signal to a first MUX of the second set of MUXes; and
the MSB of the bank select signal to each of the second set of MUXes and to an input of the second inverter;

wherein:
an output of the second inverter is applied to a second MUX of the second set of MUXes; and
the second MUX of the second set of MUXes is different than the first MUX of the second set of MUXes.

2. A computer system comprising a memory controller, the memory controller comprising:
a storage unit configured to store a data element as a base word in a first precision and for storing one or more delta words comprising additional information related to a second precision version of the stored data element,

wherein:
the data element and each of the one or more delta words is stored in a separate memory bank, and
the separate memory banks facilitate the one or more delta words to be read with the base word from the separate memory banks during a single processor cycle; and

the memory controller further comprising an access unit configured to read:
the base word and the one or more delta words of the stored data element to access the data element in the second precision; and
a second base word and a second set of one or more delta words of a second stored data element;

wherein:
the reading of the base word and delta words of the stored data element and the second stored data element occurs during a single processor cycle;
the storing unit is further configured to store one or more delta words comprising additional information related to a third precision version of the stored data element;
the second precision is higher than the first precision and the third precision is higher than the second precision;
the access unit is further configured to read the base word, the one or more delta words comprising additional information related to the second precision, and the one or more delta words comprising additional information related to the third precision to access the data element in the third precision;
each of the base word and the delta words are a width of a central processing unit register of a computer system;
the base word and each delta word are stored in different memory banks and read in parallel from the different memory banks;
a precision select signal that is usable to address the different memory banks;
the base word is a signed data word containing a sign bit;
accessing the data element in the third precision comprises adding, by a shuffling unit of a memory controller, a first set of the delta words between the sign bit and the remaining bits of the base word and adding a second set of the delta words as least significant bits;
the shuffling unit of the memory controller is further configured to split the data element into the base word and a specified precision;
the reading of the base word and the one or more delta words of the stored data element, and the second base word and the second one or more delta words of the second stored data element comprises utilizing an addressing data element;
the access unit comprises:
a first set of address components connected to a least significant bit (LSB) of a bank select signal, the first set of address components comprising a first inverter and a first set of MUXes; and
a second set of address components connected to a most significant bit (MSB) of the bank select signal, the second set of address components comprising a second inverter and a second set of MUXes;

the memory controller is further configured to apply:
the precision select signal to a first MUX of the first set of MUXes;
the LSB of the bank select signal to each of the first set of MUXes and to an input of the first inverter, wherein an output of the first inverter is applied to a first subset that does not include the first MUX of the first set of MUXes; and
the precision select signal to a first MUX of the second set of MUXes; and
the MSB of the bank select signal to each of the second set of MUXes and to an input of the second inverter;

wherein:
an output of the second inverter is applied to a second MUX of the second set of MUXes; and
the second MUX of the second set of MUXes is different than the first MUX of the second set of MUXes.

3. A computer program product comprising non-transitory

Assignees

• IBM

Inventors

• Angerer Christoph M
• Giefers Heiner
• Polig Raphael

Classifications

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F2207/382

  Reconfigurable for different fixed word lengths · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F7/38 Primary

  Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation · CPC title