Implementing 128-bit simd operations on a 64-bit datapath

Patent metadata

Field	Value
Publication number	US-2016140079-A1
Application number	US-201514940585-A
Country	US
Kind code	A1
Filing date	Nov 13, 2015
Priority date	Nov 14, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

First claim

What is claimed is:

1 . A method of implementing a processor architecture including operands of a first size and a datapath of a second size, the second size being different from the first size, the method comprising:
given a first array of registers and a second array of registers, each register of the first and second array being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size.

2 . The method of claim 1 , wherein each register of the first array corresponds with a particular register of the second array.

3 . The method of claim 2 , wherein the first register of the first array, corresponding with the second register of the second array, stores a plurality of bits of a different significance than a plurality of bits stored in the second register.

4 . The method of claim 1 , wherein selecting the first register and the second register includes selecting the first register in response to receiving a first non-null select value and selecting the second register in response to receiving a second non-null select value.

5 . The method of claim 1 , wherein selecting the first register and the second register includes selecting the first register in response to receiving a first non-null select value and not selecting the second register in the absence of receiving a second non-null select value.

6 . The method of claim 1 , further comprising:
performing a first operation on data of the first register and performing a second operation on data in the corresponding second register at a functional unit, the first operation and second operation related to a same instruction.

7 . The method of claim 1 , further comprising:
after beginning an operation on data of the first register: issuing a stall cycle; and reading data of the corresponding second register during the stall cycle.

8 . The method of claim 1 , further comprising:
returning a result of the first size, the result stored partially in a first destination register and partially in a corresponding second destination register in the first array and second array, respectively.

9 . The method of claim 1 , further comprising:
returning a result of the second size stored in a destination register in either the first array or second array.

10 . The method of claim 6 , wherein performing operations of the first size includes reading bits of a first operand in the second register in a same clock cycle as bits of a second operand in a first register when the operation is any one of a pairwise instruction and an across-vector instruction, and further includes reading bits of the first operand in a third register in a next clock cycle as bits of the second operand in a fourth register when the instruction is a pairwise instruction.

11 . The method of claim 6 , wherein performing operations of the first size includes reading bits of a plurality of registers of the second array in a first clock cycle prior to reading bits of a plurality of registers of the first array in a second clock cycle.

12 . A system for implementing a processor architecture including operands of a first size and a datapath of a second size, the second size being different from the first size, the system comprising:
a first array of registers, each register of the first array being of the second size; a second array of registers, each register of the second array being of the second size; a selection module configured to select a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size.

13 . The system of claim 12 , wherein the first array of registers and second array of registers correspond such that each register of the first array corresponds with a particular register of the second array.

14 . The system of claim 13 , wherein the first register of the first array, corresponding with the second register of the second array, stores a plurality of bits of a different significance than a plurality of bits stored in the second register.

15 . The system of claim 12 , wherein the selection module is further configured to select the first register in response to receiving a first non-null select value and select the second register in response to receiving a second non-null select value.

16 . The system of claim 12 , wherein the selection module is further configured to select the first register in response to receiving a first non-null select value and to not select the second register in the absence of receiving a second non-null select value.

17 . The system of claim 12 , further comprising:
a functional unit configured to perform a first operation on data of the first register and perform a second operation on data in the corresponding second register at a functional unit, the first operation and second operation related to a same instruction.

18 . The system of claim 12 , further comprising:
an issue unit configured to, after beginning an operation on data of the first register: issue a stall cycle and read data of the corresponding second register during the stall cycle.

19 . The system of claim 12 , further comprising:
an output module configured to return a result of the first size stored partially in a first destination register and partially in a corresponding second destination register in the first array and second array, respectively.

20 . The system of claim 12 , further comprising an output module configured to return a result of the second size stored in a destination register in either the first array or second array.

21 . The system of claim 17 , wherein the functional unit is further configured to read bits of the second register in a same clock cycle as bits of a first register based on the operation being based on at least one of a the group of a pairwise instruction and an across-vector instruction, and to read bits of the first operand in a third register in a next clock cycle as bits of the second operand in a fourth register when the instruction is a pairwise instruction.

22 . The system of claim 17 , wherein the functional unit is further configured to read bits of a plurality of registers of the second array in a first clock cycle prior to reading bits of a plurality of registers of the first array in a second clock cycle.

23 . A non-transitory computer-readable medium having computer-readable program codes embedded thereon including instructions for causing a processor to execute a method for implementing a processor architecture including operands of a first size and a datapath of a second size, the second size being different from the first size, that, when executed by one or more processors, cause the one or more processors to:
given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, select a first register and corresponding second register from the first array and second array, respectively, to perform operations of the first size.

24 . The non-transitory computer-readable medium of claim 23 , wherein the first array of registers and the second array of registers correspond such that each register of the first array corresponds with a particular register of the second array.

25 . The non-transitory computer-readable medium of

Assignees

• Cavium Inc

Inventors

• Kravitz David
• Salvi Manan
• Carlson David A

Classifications

• G06F9/30014

  with variable precision · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title

• G06F15/8007 Primary

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title