Precision data access using differential data

Patent metadata

Field	Value
Publication number	US-10430325-B2
Application number	US-201514968718-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 15, 2014
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.

First claim

What is claimed is:

1. A method for storing and reading data elements to and from a memory, the method comprising:
storing a data element as a base word in a first precision;
storing one or more delta words comprising additional information related to a second precision version of the stored data element, wherein;
the data element and each of the one or more delta words is stored in a separate memory bank, and
the separate memory banks facilitate the one or more delta words to be read with the base word from the separate memory banks during a single processor cycle;

reading the base word and the one or more delta words of the stored data element to access the data element in the second precision;
reading a second base word and a second set of one or more delta words of a second stored data element, wherein the reading of the base word and delta words of the stored data element and the second stored data element occurs during a single processor cycle; and
storing one or more delta words comprising additional information related to a third precision version of the stored data element, wherein the second precision is higher than the first precision and the third precision is higher than the second precision; and
reading the base word, the one or more delta words comprising additional information related to the second precision, and the one or more delta words comprising additional information related to the third precision to access the data element in the third precision;

wherein:
each of the base word and the delta words are a width of a central processing unit register of a computer system;
the base word and each delta word are stored in different memory banks and read in parallel from the different memory banks;
the base word is a signed data word containing a sign bit;
accessing the data element in the third precision comprises adding, by a shuffling unit of a memory controller, a first set of the delta words between the sign bit and the remaining bits of the base word and adding a second set of the delta words as least significant bits;

wherein:
the reading of the base word and the one or more delta words of the stored data element, and the second base word and the second one or more delta words of the second stored data element, comprises utilizing an addressing data element;
an access unit comprises:
a first set of address components connected to a least significant bit (LSB) of a bank select signal, the first set of address components comprising a first inverter and a first set of MUXes; and
a second set of address components connected to a most significant bit (MSB) of the bank select signal, the second set of address components comprising a second inverter and a second set of MUXes;

the method further comprising the memory controller:
applying a precision select signal to a first MUX of the first set of MUXes;
applying the LSB of the bank select signal to each of the first set of MUXes and to an input of the first inverter, wherein an output of the first inverter is applied to a first subset that does not include the first MUX of the first set of MUXes;
applying the precision select signal to a first MUX of the second set of MUXes;
applying the MSB of the bank select signal to each of the second set of MUXes and to an input of the second inverter;

wherein:
an output of the second inverter is applied to a second MUX of the second set of MUXes; and
the second MUX of the second set of MUXes is different than the first MUX of the second set of MUXes.

2. The method according to claim 1 , wherein the data element is accessed in a precision between the precision of the base word and the second precision when a first subset of delta words of the one or more delta words are read from the memory.

3. The method according to claim 1 , wherein the one or more delta words are added as least significant bits to the base word.

4. The method according to claim 1 , wherein a first part of the delta words is added as most significant bits to the base word and a second part of the delta words is added as least significant bits.

5. The method according to claim 1 , wherein the data element is stored in a third precision using a different number of delta words than used for the second precision.

6. The method according to claim 1 , wherein:
the one or more delta words is one delta word; and
accessing the data element in the second precision comprises adding, by the shuffling unit of the memory controller, a first half of the delta word between the sign bit and the remaining bits of the base word and adding, by the shuffling unit of the memory controller, a second half of the delta word as least significant bits.

7. The method according to claim 1 , further comprising:
prior to storing the base word and the one or more delta words, splitting, by the shuffling unit of the memory controller, the data element in the second precision into the base word and the one or more delta words, wherein accessing the data element in the second precision comprises reordering, by the shuffling unit of the memory controller, the base word and the one or more delta words into the data element in the second precision.

8. The method of claim 1 , wherein the data element is accessible in the first precision by reading only the base word.

9. The method of claim 1 , wherein:
each of the first set of MUXes comprises inputs connected to: two fixed-value signals and the LSB of the bank select signal;
each of the first subset of MUXes comprises an input connected to the output of the first inverter;
the second MUX comprises inputs connected to: one fixed-value signal and the MSB of the bank select signal; and
the second MUX comprises an input connected to the output of the second inverter.

10. The method of claim 9 , wherein:
the MSB of the bank select signal is connected to a plurality of inputs of each of the second set of MUXes that do not include the second MUX.

11. The method of claim 9 , wherein:
the second MUX comprises a plurality of inputs connected to the output of the second inverter.

Assignees

• IBM

Inventors

• Angerer Christoph M
• Giefers Heiner
• Polig Raphael

Classifications

• G06F2207/382

  Reconfigurable for different fixed word lengths · CPC title

• G06F2212/72

  Details relating to flash memory management · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F9/3013 Primary

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title