Failure recovery apparatus of digital logic circuit and method thereof

Patent metadata

Field	Value
Publication number	US-2016019126-A1
Application number	US-201514749558-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Jul 21, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.

First claim

What is claimed is:

1 . A failure recovery apparatus of digital logic circuit comprising:
a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having the first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having the second cycle which is longer than the first cycle when it is determined as that a fault occurs.

2 . The failure recovery apparatus of claim 1 , wherein the fault detection block comprises a comparator configured to compare output logical values of the plurality of digital logic circuit, recognize as a fault occurrence when the output logical values are different, and report the fault occurrence to the failure recovery block.

3 . The failure recovery apparatus of claim 1 , wherein the failure recovery block comprises a failure recovery unit configured to be used for executing a program for failure recovery, wherein the failure recovery unit comprises:
a plurality of combinational logic circuit configured to perform a failure recovery operation; and a plurality of delay signal generator configured to output one logical value by receiving an output logical value of any one combinational logic circuit among the plurality of combinational logic circuit and N number of clocks having the second cycle in which N is a natural number.

4 . The failure recovery apparatus of claim 3 , wherein the delay signal generator comprises one flip-flop configured to receive the output logical value of any one combinational logic circuit and the one clock having the second cycle.

5 . The failure recovery apparatus of claim 4 , wherein the failure recovery block further comprises a clock generator configured to generate the one clock having the second cycle.

6 . The failure recovery apparatus of claim 3 , wherein the delay signal generator comprises:
N number of flip-flops configured to receive the output logical value of any one combinational logic circuit commonly and receive any one among N number of clocks having phase difference each other; and a voter configured to receive output logical values of the N number of flip-flops, and select and output a logical value corresponding to majority among the received output logical values.

7 . The failure recovery apparatus of claim 6 , wherein the failure recovery block further comprises a clock generator configured to generate the N number of clocks having the second cycle and phase difference each other.

8 . The failure recovery apparatus of claim 6 , wherein phase difference between the n−1 th clock in which 2≦n<N and the n th clock among the N number of clocks is different from that between the n th clock and the n+1 th clock.

9 . The failure recovery apparatus of claim 3 , wherein the failure recovery unit is positioned outside of the plurality of digital logic circuit.

10 . The failure recovery apparatus of claim 3 , wherein the failure recovery unit is positioned inside of any one of the plurality of digital logic circuit.

11 . The failure recovery apparatus of claim 10 , wherein the failure recovery block further comprises a clock generator configured to generate a clock having the first cycle to output it to the plurality of digital logic circuit before the fault is detected and to generate a clock having the second cycle to output it to the failure recovery unit after the failure is detected.

12 . The failure recovery apparatus of claim 3 , wherein the failure recovery block further comprises an initialization unit configured to initialize the plurality of digital logic circuit and the failure recovery unit when the failure is detected.

13 . A failure recovery method of digital logic circuit comprising:
determining fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having the first cycle; and performing a failure recovery operation of the plurality of digital logic circuit by using a clock having the second cycle which is longer than the first cycle when it is determined as that a fault occurs.

Assignees

• Korea Electronics Telecomm

Inventors

• Kwon Young-Su

Classifications

• G06F11/2028 Primary

  eliminating a faulty processor or activating a spare · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G06F11/1658

  Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit · CPC title

• G06F11/1438

  Restarting or rejuvenating · CPC title

• G06F11/1641 Primary

  where the comparison is not performed by the redundant processing components · CPC title