Switching power converter, clock module, control circuit and associated control method

Patent metadata

Field	Value
Publication number	US-9641085-B2
Application number	US-201514630215-A
Country	US
Kind code	B2
Filing date	Feb 24, 2015
Priority date	Feb 25, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

A power converter having a clock module and a method for controlling a clock signal of the power converter. The clock module is configured to provide the clock signal and to set a clock frequency of the clock signal to a first predetermined frequency at the moment when the power converter is powered on. The clock module is further configured to regulate the clock frequency to increase from the first predetermined frequency to a second predetermined frequency through a predetermined times of step type frequency increase during a startup procedure of the power converter.

First claim

I claim:

1. A clock module for providing a clock signal to a power converter, wherein the power converter has a startup procedure beginning at the moment when the power converter is powered on and ending when an output voltage of the power converter arrives at a desired steady state value, the clock module comprising:
a clock generator, having a clock control terminal and a clock output terminal, wherein the clock control terminal is configured to receive a frequency regulation signal, and wherein the clock generator is configured to provide the clock signal at the clock output terminal, and wherein the clock signal has a sequence of clock pulses and a clock frequency; and
a clock frequency modulator, having a modulator input terminal and a modulator output terminal, wherein the modulator input terminal is configured to receive the clock signal, and wherein the clock frequency modulator is configured to perform a timing based on the pulses of the clock signal and to provide the frequency regulation signal at the modulator output terminal based on the timing, and wherein the frequency regulation signal is configured to set the clock frequency at a first predetermined frequency at the moment when the power converter is powered on, and to regulate the clock frequency to increase from the first predetermined frequency to a second predetermined frequency through a predetermined times of step type frequency increase during the startup procedure.

2. The clock module of claim 1 , wherein
the clock frequency modulator is further configured to regulate the clock frequency to increase with a predetermined frequency increment for each time of step type frequency increase.

3. The clock module of claim 1 , wherein for each time of step type frequency increase, the clock frequency has a pre-increase frequency before that time of step type frequency increase and a post-increase frequency after that time of step type frequency increase, and wherein
the clock frequency modulator is further configured to set the pre-increase frequency for the first time of step type frequency increase to the first predetermined frequency; and wherein
the clock frequency modulator is further configured to set the post-increase frequency for the last time of step type frequency increase to the second predetermined frequency; and wherein
the clock frequency modulator is further configured to regulate the pre-increase frequency for each time of step type frequency increase to last for a predetermined duration.

4. The clock module of claim 1 , wherein the frequency regulation signal has an initial state and a predetermined number of frequency regulation state, and wherein the predetermined number of frequency regulation states are respectively corresponding to the predetermined times of step type frequency increase, and wherein
the clock frequency modulator is configured to set the clock frequency to the first predetermined frequency at the initial state of the frequency regulation signal, and wherein
the clock frequency modulator is further configured to regulate the clock frequency to conduct a step type frequency increase each time the frequency regulation signal changes from one frequency regulation state to another frequency regulation state.

5. The clock module of claim 4 , wherein the clock frequency modulator is configured to change the frequency regulation signal from one frequency regulation state to another frequency regulation state every time the timing reaches M pulses of the clock signal, and wherein M is a positive integer.

6. The clock module of claim 4 , wherein:
the predetermined times is set to 2 N −1, wherein N is a positive integer; and wherein
the predetermined number is set to 2 N −1; and wherein
the clock frequency modulator comprises:
an N-bit binary up counter, having a clock input terminal and N-bit output terminals, wherein the clock input terminal is configured to receive the clock signal, and wherein the N-bit output terminals are respectively the 0 th to the (N−1) th bit output terminals from the lowest precedence to the highest precedence, and are respectively configured to output a 0 th to a (N−1) th binary bit signals of the N-bit binary up counter, and wherein each of the 0 th to the (N−1) th binary bit signals has a logic “0” state and a logic “1” state making a combination of the 0 th to the (N−1) th binary bit signals to have 2 N logic states, wherein the 2 N logic states comprise a logic “0” initial state used as the initial state of the frequency regulation signal, and (2 N −1) other logic states used as the (2 N− 1) frequency regulation states of the frequency regulation signal, and wherein the N-bit binary counter is configured to perform an up counting to change the combination of the 0 th to the (N−1) th binary bit signals from one logic state to another among the 2 N logic states for once in response to each pulse of the clock signal, starting from the logic “0” initial state; and wherein

the clock generator comprises:
a clock generation module at least comprising a constant current source and a capacitor, wherein the clock generation module is configured to generate the clock signal at least partially based on charging and discharging of the capacitor by the constant current source, and wherein the constant current source is configured to provide a first constant current, and wherein the first constant current is configured to determine the first predetermined frequency; and
a controllable current source module having N controllable current sources referred to as the 0 th to the (N−1) th controllable current sources, wherein the 0 th to the (N−1) th controllable current sources are respectively electrically coupled to the capacitor and in parallel with the first constant current source; and wherein,
for each j=0, 1, 2, . . . , N−1, the j th controllable current source may have a j th current control terminal and a j th current output terminal, wherein the j th current control terminal is configured to receive the j th binary bit signal generated at the j th output terminal of the N-bit binary up counter, and wherein j th controllable current source is configured to to provide a j th current to the j th current output terminal in response the logic “1” state of the j th binary bit signal, and wherein the j th current is set to be a multiple of the first constant current with a j th predetermined current multiple factor.

7. The clock module of claim 4 , wherein:
the predetermined times is set to 2 N −1, wherein N is a positive integer; and wherein
the predetermined number is set to 2 N −1; and wherein
the clock frequency modulator comprises:
an N-bit binary down counter, having a clock input terminal and N-bit output terminals, wherein the clock input terminal is configured to receive the clock signal, and wherein the N-bit output terminals are respectively the 0 th to the (N−1) th bit output terminals from the lowest precedence to the highest precedence, and are respectively configured to output a 0 th to a (N−1) th binary bit signals of the N-bit binary down counter, and wherein each of the 0 th to the (N−1) th binary bit signals has a logic “0” state and a logic “1” state making a combination of the 0 th to the (N−1) th binary bit signals to have 2 N logic states, wherein the 2 N logic states comprise a logic “1” initial state used as the initial state of the frequency regulation signal, and (2 N −1) other logic states used as the (2 N− 1) frequency regulation states of the frequency regulation signal, and wherein the N-bit binary counter is configured to perform a down counting to change the combination of the 0 th to the (N−1) th binary bit signals from one logic state to another among the 2 N logic states for once i

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Li Yike

Classifications

• H02M3/33507 Primary

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• H02M1/36

  Means for starting or stopping converters · CPC title

• H03K21/08

  Output circuits · CPC title

• H03K23/667

  by switching the base during a counting cycle · CPC title