Frequency divider with duty cycle adjustment within feedback loop

Patent metadata

Field	Value
Publication number	US-9379722-B2
Application number	US-201313926631-A
Country	US
Kind code	B2
Filing date	Jun 25, 2013
Priority date	Jun 25, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

First claim

What is claimed is:

1. An apparatus comprising:
multiple divider circuits ( 610 a , 610 k ) coupled in a feedback loop, and each divider circuit configured to receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, the second frequency being a fraction of the first frequency; and
multiple duty cycle adjustment circuits ( 620 a , 620 k ) each coupled to respective divider circuits within the feedback loop and configured to adjust duty cycle of the at least one divided signal provided by one of the divider circuits and provide at least one duty cycle adjusted signal to another one of the divider circuits, wherein the feedback loop is configured to have a last one of the duty cycle adjustment circuits provide its duty cycle adjusted signal to a first one of the divider circuits;
wherein a component of the at least one of the multiple divider circuits receives the clock signal at a noninverting input and an inverting input to provide an output at a coupled node.

2. The apparatus of claim 1 , the multiple divider circuits comprising:
a first latch ( 310 a ) configured to receive the clock signal and provide a first divided signal; and
a second latch ( 310 b ) configured to receive the clock signal and provide a second divided signal.

3. The apparatus of claim 2 , the multiple duty cycle adjustment circuits comprising:
a first duty cycle adjustment circuit ( 320 a ) configured to receive the first divided signal from the first latch and provide a first duty cycle adjusted signal to the second latch; and
a second duty cycle adjustment circuit ( 320 b ) configured to receive the second divided signal from the second latch and provide a second duty cycle adjusted signal to the first latch.

4. The apparatus of claim 3 , the first duty cycle adjustment circuit comprising:
an inverter ( 434 ) configured to receive an adjustable bias current and provide the first duty cycle adjusted signal having an adjustable duty cycle determined based on the adjustable bias current.

5. The apparatus of claim 4 , the first duty cycle adjustment circuit further comprising:
a duty cycle controller ( 436 ) configured to receive a duty cycle control signal and provide the adjustable bias current for the inverter.

6. The apparatus of claim 5 , the duty cycle controller comprising:
a look-up table ( 532 ) configured to receive the duty cycle control signal and provide at least one control signal; and
a bias current generator ( 534 ) configured to receive the at least one control signal and provide the adjustable bias current for the inverter.

7. The apparatus of claim 3 , the first latch configured to further receive the second duty cycle adjusted signal and provide the first divided signal.

8. The apparatus of claim 7 , the first latch configured to further receive the second divided signal from the second latch and provide the first divided signal.

9. The apparatus of claim 3 , the first and second latches and the first and second duty cycle adjustment circuits configured to perform divide-by-2, and the second frequency being one half of the first frequency.

10. The apparatus of claim 3 , the first divided signal comprising an inphase divided signal and the second divided signal comprising a quadrature divided signal.

11. The apparatus of claim 1 , wherein a number of divider circuits is greater than a number of duty cycle adjustment circuits.

12. A method of generating a frequency divided signal, comprising:
generating ( 712 ) at least one divided signal with multiple divider circuits coupled in a feedback loop, each divider circuit receiving a clock signal at a first frequency and providing the at least one divided signal at a second frequency, the second frequency being a fraction of the first frequency; and
generating ( 714 ) at least one duty cycle adjusted signal to be provided to one divider circuit by adjusting duty cycle of the at least one divided signal provided by another divider circuit with multiple duty cycle adjustment circuits, each duty cycle adjustment circuit coupled to respective divider circuits within the feedback loop, wherein the feedback loop is configured to have a last one of the duty cycle adjustment circuits provide its duty cycle adjusted signal to a first one of the divider circuits;
wherein a component of the at least one of the multiple divider circuits receives the clock signal at a noninverting input and an inverting input to provide an output at a coupled node.

13. The method of claim 12 , the multiple divider circuits comprising first and second latches, the generating the at least one divided signal comprising:
generating a first divided signal with the first latch; and generating a second divided signal with the second latch.

14. The method of claim 13 , the multiple duty cycle adjustment circuits comprising first and second duty cycle adjustment circuits, the generating the at least one duty cycle adjusted signal comprising:
generating a first duty cycle adjusted signal with the first duty cycle adjustment circuit; and
generating a second duty cycle adjusted signal with the second duty cycle adjustment circuit.

15. The method of claim 14 , the first duty cycle adjustment circuit comprising an inverter, the generating the first duty cycle adjusted signal comprising:
generating the first duty cycle adjusted signal having an adjustable duty cycle determined based on an adjustable bias current of the inverter.

16. The method of claim 15 , further comprising:
generating the adjustable bias current for the inverter based on a duty cycle control signal.

17. The method of claim 15 , further comprising:
generating at least one control signal based on a duty cycle control signal; and generating the adjustable bias current for the inverter based on the at least one control signal.

18. An apparatus comprising:
multiple means for receiving a clock signal at a first frequency and generating at least one divided signal at a second frequency based on the clock signal, the second frequency being a fraction of the first frequency; and
multiple means for generating at least one duty cycle adjusted signal by adjusting duty cycle of the at least one divided signal, each means for generating the at least one duty cycle adjusted signal being coupled to respective means for receiving the clock signal in a feedback loop, wherein the feedback loop is configured to have a last of the means for generating at least one duty cycle adjusted signal provide its duty cycle adjusted signal to a first of the means for receiving the clock signal;
wherein a component of the at least one of the multiple means for receiving receives the clock signal at a noninverting input and an inverting input to provide an output at a coupled node.

19. The apparatus of claim 18 , the multiple means for generating the at least one divided signal comprising:
first latching means configured to generate a first divided signal; and
second latching means configured to generate a second divided signal.

20. The apparatus of claim 19 , the multiple means for generating the at least one duty cycle adjusted signal comprising:
first duty cycle adjustment means configured to generate a first duty cycle adjusted signal; and
second duty cycle adjustment means configured to generate a second duty cycle adjusted signal.

21. The apparatus of claim 20 , the first duty cycle adjustment means configured to generate the first duty cycle adjusted signal ha

Assignees

• Qualcomm Inc

Inventors

• Chen Wu-Hsin
• Sridhara Sriramgopal
• Liu Li

Classifications

• H03L7/18 Primary

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K21/08

  Output circuits · CPC title

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title