Semiconductor package metal shadowing checks

Patent metadata

Field	Value
Publication number	US-10423752-B2
Application number	US-201715719743-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

First claim

What is claimed is:

1. A computer-implemented method for checking metal coverage in a laminate structure, the method comprising:
receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines;
mapping each metal power shape to one or more cells in a two-dimensional array;
determining, for each signal line, whether the metal power shapes satisfy the metal shadowing rules; and
displaying on a user interface a list of signal lines that do not satisfy the metal shadowing rules.

2. The method of claim 1 , wherein the plurality of laminate layers comprises a topmost laminate layer, a core laminate layer, and a bottommost laminate layer.

3. The method of claim 2 , further comprising:
for each signal line in a laminate layer above the core laminate layer:
mapping the signal line to one or more cells in a two-dimensional array; and
determining whether the metal power shapes above the signal line satisfy the metal shadowing rules.

4. The method of claim 2 , further comprising:
for each signal line in a laminate layer below the core laminate layer:
mapping the signal line to one or more cells in a two-dimensional array; and
determining whether the metal power shapes below the signal line satisfy the metal shadowing rules.

5. The method of claim 1 , wherein the metal shadowing rules comprise a single layer metal power shape-to-signal line minimum overlap distance.

6. The method of claim 5 , wherein the metal shadowing rules comprise a multiple layer metal power shape-to-metal power shape minimum overlap distance.

7. The method of claim 1 , wherein each cell in the two-dimensional array comprises a 32 digit binary number and each digit in the 32 digit binary number corresponds to a unique location on a laminate layer in the semiconductor package design.

8. The method of claim 7 , wherein each unique location is a two micron by two micron pixel.

9. The method of claim 8 , wherein mapping each metal power shape to one or more cells in a two-dimensional array comprises setting the value of all binary digits in each of the cells in the two-dimensional array to 0 or 1, wherein a value of 1 indicates a presence of a metal power shape.

10. A system for checking metal coverage in a laminate structure, the system having a processor coupled to a memory, the processor configured to:
receive metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines;
map each metal power shape to one or more cells in a two-dimensional array;
determine, for each signal line, whether the metal power shapes satisfy the metal shadowing rules; and
display on a user interface a list of signal lines that do not satisfy the metal shadowing rules.

11. The system of claim 10 , wherein the plurality of laminate layers comprises a topmost laminate layer, a core laminate layer, and a bottommost laminate layer.

12. The system of claim 11 , further comprising:
for each signal line in a laminate layer above the core laminate layer:
map the signal line to one or more cells in a two-dimensional array; and
determine whether the metal power shapes above the signal line satisfy the metal shadowing rules.

13. The system of claim 11 , further comprising:
for each signal line in a laminate layer below the core laminate layer:
map the signal line to one or more cells in a two-dimensional array; and
determine whether the metal power shapes below the signal line satisfy the metal shadowing rules.

14. The system of claim 11 , wherein the metal shadowing rules comprise a single layer metal power shape-to-signal line minimum overlap distance.

15. The system of claim 14 , wherein the metal shadowing rules comprise a multiple layer metal power shape-to-metal power shape minimum overlap distance.

16. A computer program product for checking metal coverage in a laminate structure, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
receive metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines;
map each metal power shape to one or more cells in a two-dimensional array;
determine, for each signal line, whether the metal power shapes satisfy the metal shadowing rules; and
display on a user interface a list of signal lines that do not satisfy the metal shadowing rules.

17. The computer program product of claim 16 , wherein each cell in the two-dimensional array comprises a 32 digit binary number and each digit in the 32 digit binary number corresponds to a unique location on a laminate layer in the semiconductor package design.

18. The computer program product of claim 17 , wherein each unique location is a two micron by two micron pixel.

19. The computer program product of claim 18 , wherein mapping each metal power shape to one or more cells in a two-dimensional array comprises setting the value of all binary digits in each of the cells in the two-dimensional array to 0 or 1, wherein a value of 1 indicates a presence of a metal power shape.

20. The computer program product of claim 16 , wherein the plurality of laminate layers comprises a topmost laminate layer, a core laminate layer, and a bottommost laminate layer.

Assignees

• IBM

Inventors

• Call Anson J
• Preda Francesco
• Walling Paul R

Classifications

• G06F2113/20

  Packaging, e.g. boxes or containers · CPC title

• G06F2113/18

  Chip packaging · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2111/10

  Numerical modelling · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title