Memory controller, control method for the memory controller, and control method for memory

Patent metadata

Field	Value
Publication number	US-10423548-B2
Application number	US-201715853655-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Nov 17, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

First claim

What is claimed is:

1. A memory controller accessing a memory comprising a plurality of memory blocks, comprising:
a storage circuit storing a first refresh value and a first data table; and
a control circuit accessing the memory blocks and changing the first data table according to a plurality of external commands, wherein the first data table comprises a plurality of bits, and each bit has a value that indicates whether a corresponding memory block stores valid data,
wherein in a refresh mode, the control circuit selects a specific memory block among the memory blocks according to the first refresh value and determines whether the specific memory block stores valid data according to the first data table,
wherein when the specific memory block stores valid data, the control circuit sends a refresh command to the memory and, after a first waiting time, the control circuit continuously accesses the memory,
wherein when the specific memory block does not store any data or stores invalid data, the control circuit sends the refresh command and, after a second waiting time, the control circuit continuously accesses the memory,
wherein the second waiting time is shorter than the first waiting time.

2. The memory controller as claimed in claim 1 , wherein the control circuit sends the refresh command to the memory according to an input clock, the first waiting time is longer than a clock cycle of the input clock, and the second waiting time is equal to the clock cycle.

3. The memory controller as claimed in claim 1 , wherein during the first waiting time, the memory performs a refresh operation on the specific memory block, and during the second waiting time, the memory does not perform the refresh operation on the specific memory block.

4. The memory controller as claimed in claim 1 , wherein the storage circuit comprises:
a refresh address register configured to store the first refresh value.

5. The memory controller as claimed in claim 1 , wherein the storage circuit comprises:
a counter circuit having a counter value, wherein the counter value serves as the first refresh value.

6. The memory controller as claimed in claim 5 , wherein after the first waiting time, the control circuit updates the counter value.

7. The memory controller as claimed in claim 1 , wherein in a write mode, the control circuit sends a write command to the memory to write external data to at least one of the memory blocks, and in the write mode, the control circuit updates the first data table according to a write address of the write command.

8. The memory controller as claimed in claim 1 , wherein in a read mode, the control circuit sends a read command to the memory to read at least one of the memory blocks, and in the read mode, the control circuit does not change the first data table.

9. The memory controller as claimed in claim 1 , wherein when the control circuit receives an eviction command, the control circuit updates the first data table according to an eviction address of the eviction command.

10. The memory controller as claimed in claim 1 , wherein when the control circuit receives a flush command, the control circuit updates the first data table according to a flush address of the flush command.

11. The memory controller as claimed in claim 1 , wherein the memory stores a second refresh value and a second data table, the second refresh value is the same as the first refresh value, and the second data table is the same as the first data table.

12. A control method for a memory controller which accesses a memory comprising a plurality of memory blocks, comprising:
determining whether a refresh request is issued;
when the refresh request is issued, a refresh value is read to select a specific memory block among the memory blocks;
reading a data table to determine whether the specific memory block stores valid data;
sending a refresh command to the memory and, after a first waiting time, accessing the memory when the specific memory block stores valid data;
sending the refresh command to the memory and, after a second waiting time, accessing the memory when the specific memory block does not store any data or stores invalid data; and
updating the refresh value,
wherein the second waiting time is shorter than the first waiting time.

13. The control method as claimed in claim 12 , further comprising:
sending the refresh command to the memory according to an input clock, wherein the first waiting time is longer than a clock cycle of the input clock, and the second waiting time is equal to the clock cycle of the input clock.

14. The control method as claimed in claim 12 , wherein during the first waiting time, the memory performs a refresh operation on the specific memory block, and during the second waiting time, the memory does not perform the refresh operation on the specific memory block.

15. The control method as claimed in claim 12 , further comprising:
disposing a counter circuit in the memory controller, wherein the counter circuit has a counter value, and the counter value is provided as the refresh value.

16. The control method as claimed in claim 15 , wherein when the refresh request is issued, the counter value is updated.

17. The control method as claimed in claim 15 , further comprising:
during an initial period, resetting the data table and the refresh value.

18. The control method as claimed in claim 12 , further comprising:
in a write mode:
sending a write command to the memory to write external data to at least one of the memory blocks; and
updating the data table according to a write address of the write command.

19. The control method as claimed in claim 12 , further comprising:
in a read mode:
sending a read command to the memory to read at least one of the memory blocks, wherein the data table is not changed.

20. The control method as claimed in claim 12 , further comprising:
determining whether an eviction command is received, wherein when the eviction command is received, the data table is updated according to an eviction address of the eviction command.

21. The control method as claimed in claim 12 , further comprising:
determining whether a flush command is received, wherein when the flush command is received, the data table is updated according to a flush address of the flush command.

22. A memory coupled to a memory controller, comprising:
a plurality of memory blocks configured to store data;
a storage circuit storing a first refresh value and a first data table; and
a control circuit accessing the memory blocks and updating the first data table, wherein the first data table comprises a plurality of bits, and each bit indicates whether a corresponding memory block stores valid data,
wherein when the control circuit receives a refresh command, the control circuit selects a specific memory block among the memory blocks according to the first refresh value and determines whether the specific memory block stores valid data according to the first data table,
wherein when the specific memory block stores valid data, the control circuit refreshes the specific memory block, and
wherein when the specific memory block does not store any data or stores invalid data, the control circuit does not refresh the specific memory block.

23. The memory as claimed in claim 22 , wherein the storage circuit comprises:
a refresh address register configured to store the first refresh value.

24. The memory

Assignees

• Ind Tech Res Inst

Inventors

• Lo Chih-Yen
• Lai Jenn-Shiang

Classifications

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title