Semiconductor memory device that controls refresh period, memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-9490001-B2
Application number	US-201313937747-A
Country	US
Kind code	B2
Filing date	Jul 9, 2013
Priority date	Jul 12, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a cell array; and
a refresh controller coupled to the cell array and configured to insert additional insertion refresh addresses in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array at a fixed refresh rate, wherein the refresh controller comprises:
an address generator configured to generate the insertion refresh addresses; and
a timing detector configured to detect a timing for performing an insertion refresh by counting a number of refresh operations performed in the first refresh address sequence, to designate additional sequence locations for periodic insertion of successive ones of the insertion refresh addresses in the first refresh address sequence, and to control the address generator responsive thereto, wherein the designated additional sequence locations are distributed at uniform intervals within the second refresh address sequence.

2. The semiconductor memory device of claim 1 , wherein the refresh controller further comprises an address selector configured to receive the first refresh address sequence and the insertion refresh addresses and to selectively output the insertion refresh addresses and addresses from the first refresh address sequence responsive to the timing detector.

3. The semiconductor memory device of claim 1 , wherein the timing detector comprises:
a first counter configured to perform a counting operation in response to a refresh control signal and to output a first signal when a first value is counted; and
a second counter configured to perform a counting operation in response to the first signal and to output a second signal to access address information stored by the address generator.

4. The semiconductor memory device of claim 1 , wherein the refresh controller is configured to store an address of a cell region having a relatively inferior data retention characteristic and to output the stored address information as an insertion refresh address.

5. The semiconductor memory device of claim 1 , wherein the refresh controller is further configured to store master information indicating whether to perform an insertion refresh operation.

6. The semiconductor memory device of claim 5 , wherein the refresh controller further comprises an enable controller configured to receive the master information and to enable and disable refresh address insertion according to a state of the master information.

7. The semiconductor memory device of claim 1 , wherein the cell array comprises N-cell groups, and each of the N-cell groups comprises a plurality of cell regions, wherein the refresh controller is configured to store address information about a number of cells less than N and, during one refresh period, to refresh each cell of an N-cell group at least once and refresh less than N cells at least twice.

8. The semiconductor memory device of claim 7 , wherein each of the plurality of cell regions is a page that is selected in response to one row address.

9. The semiconductor memory device of claim 1 , wherein the refresh controller further comprises:
a command decoder configured to generate an internal refresh command by decoding an external command; and
a refresh control circuit generating a refresh control signal in response to the internal refresh command.

10. A semiconductor memory device comprising:
a memory cell array comprising at least one N-cell region;
an address counter configured to generate at least one first refresh address designating the at least one N-cell region for a refresh operation;
an address generator configured to generate a second refresh address designating at least one cell region of the at least one N-cell region for the refresh operation;
a timing detector configured to detect an output timing for the second refresh address by counting a number of refresh operations performed by using the first refresh address, wherein the timing detector is configured to:
count a number of refresh operations performed in a first refresh address sequence; and
designate a sequence location of an insertion of the second refresh address with respect to the first refresh address sequence at one of a plurality of periodic positions in the first refresh address sequence; and

an address selector configured to receive the first and second refresh addresses and to selectively output the first and second refresh addresses during the refresh operation, wherein the address selector is configured to selectively output the first refresh address and the second refresh address responsive to the output of the timing detector.

11. The semiconductor memory device of claim 10 , wherein the address generator comprises:
an address table configured to store the second refresh address and to output the second refresh address responsive to an output of the timing detector.

12. The semiconductor memory device of claim 11 , wherein the address selector is configured to selectively output the first refresh address and the second refresh address responsive to the output of the timing detector.

13. The semiconductor memory device of claim 10 , wherein the address generator is configured to store second refresh addresses corresponding to A cell regions of the at least one N-cell region and wherein the address selector is configured to output N first refresh addresses and A second refresh addresses during the refresh operation.

14. A refreshing method performed by a semiconductor memory device comprising a plurality of cell regions, the refreshing method comprising:
outputting a plurality of first addresses based on a counting operation and a plurality of second addresses from a storing unit that stores address information about at least one cell region from among the plurality of cell regions;
performing a plurality of first refresh operations on a first cell group comprising N cell regions by using a first portion of the plurality of first addresses based on a counting operation;
performing a second refresh operation according to a periodic interval on the at least one cell region by using one of the second addresses;
performing a plurality of first refresh operations on a second cell group comprising other ones of the N cell regions by using a second portion of the plurality of first addresses; and
performing a second refresh operation according to the periodic interval on another cell region by using another one of the second addresses after performing the plurality of first refresh operations on the second cell group;
wherein alternate performing of first refresh operations on the plurality of cell regions by using the plurality of first addresses and second refresh operations on a selected portion of the plurality of cell regions by using the second addresses is completed in a refresh period.

15. The refreshing method of claim 14 , wherein, during a refresh period, a first refresh operation on the plurality of cell regions and a second refresh operation on some of the plurality of cell regions are performed.

16. The refreshing method of claim 14 , wherein a refresh period value of the repeating periodic interval varies according to the number of cell regions on which the second refresh operation is performed.

17. The refreshing method of claim 14 , further comprising:
receiving an external command for a start of an refresh mode; and
decoding the external command, thereby generating a refresh control signal,
wherein the first address is

Assignees

• Kim Jung-Sik
• Kim Cheol
• Shin Sang-Ho
• Samsung Electronics Co Ltd

Inventors

• Kim Jung-Sik
• Kim Cheol
• Shin Sang-Ho

Classifications

• G11C11/40622 Primary

  Partial refresh of memory arrays · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/402

  with charge regeneration individual to each memory cell, i.e. internal refresh · CPC title

• G11C2211/406

  Refreshing of dynamic cells · CPC title