Analog-to-digital conversion circuit and method

Patent metadata

Field	Value
Publication number	US-10411725-B2
Application number	US-201816168774-A
Country	US
Kind code	B2
Filing date	Oct 23, 2018
Priority date	Mar 30, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an i th conversion at a conversion stage, the logic circuit controls, the lower electrode plate of an i th capacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1 th flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array.

First claim

What is claimed is:

1. An analog-to-digital conversion circuit, comprising a first capacitor array, a logic circuit and a comparator; wherein:
at a sampling stage, the first capacitor array is configured to connect lower electrode plates of N capacitors in the first capacitor array to a first input voltage, connect lower electrode plates of the other capacitors in the first capacitor array to a common-mode voltage, and connect upper electrode plates of all capacitors in the first capacitor array to the common-mode voltage to sample the first input voltage, wherein N is a positive integer less than a total number of the capacitors in the first capacitor array;
in an i th conversion at a conversion stage, the logic circuit is configured to control, according to an i th stored flag bit, the lower electrode plate of an i th capacitor in the first capacitor array to connect to a reference voltage or a ground voltage, such that a first comparison voltage output by the first capacitor array approximates a second comparison voltage, wherein i is a positive integer less than the total number of the capacitors in the first capacitor array; and
the comparator is configured to store a comparison result between the first comparison voltage and the second comparison voltage to an i+1 th flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of the capacitors in the first capacitor array.

2. The circuit according to claim 1 , further comprising:
at a pre-conversion stage, the first capacitor array is configured to connect the lower electrode plates of all the capacitors to the common-mode voltage, and connect the upper electrode plates of all the capacitors in the first capacitor array to the comparator to supply the first comparison voltage to the comparator, wherein the pre-conversion stage is between the sampling stage and a first conversion at the conversion stage; and
the comparator is configured to store the comparison result between the first comparison voltage and the second comparison voltage to a first flag bit in the logic circuit.

3. The circuit according to claim 1 , wherein the comparator is connected to the common-mode voltage to use the common-mode voltage as the second comparison voltage.

4. The circuit according to claim 1 , wherein the flag bit stored in the logic circuit takes a value of 0 or 1.

5. The circuit according to claim 4 , wherein the controlling, by the logic circuit according to an i th stored flag bit, the lower electrode plate of an i th capacitor in the first capacitor array to connect to a reference voltage or a ground voltage comprises:
if the flag bit is 1, connecting the lower electrode plate of the i th capacitor in the first capacitor array to the ground voltage; and
if the flag bit is 0, connecting the lower electrode plate of the i th capacitor in the first capacitor array to the reference voltage.

6. The circuit according to claim 4 , wherein the comparator is specifically configured to define the comparison result to 1 if the first comparison voltage is greater than the second comparison result, and define the comparison result to 0 if the first comparison voltage is not greater than the second comparison result.

7. The circuit according to claim 1 , wherein the common-mode voltage is an average value of the reference voltage and the ground voltage.

8. The circuit according to claim 1 , wherein the logic circuit is a shift register.

9. The circuit according to claim 1 , wherein the value of N is defined according to a value range of the first input voltage.

10. The circuit according to claim 1 , wherein the first capacitor array is a binary capacitor array or a non-binary capacitor array.

11. The circuit according to claim 1 , further comprising a second capacitor array; wherein
at the sampling stage, the second capacitor array is configured to connect lower electrode plates of N capacitors in the second capacitor array to a second input voltage, connect lower electrode plates of the other capacitors in the second capacitor array to a common-mode voltage, and connect upper electrode plates of all the capacitors in the second capacitor array to the common-mode voltage to sample the second input voltage, wherein the N capacitors in the second capacitor array correspond to the N capacitors in the first capacitor array; and
in the i th conversion at the conversion stage, the logic circuit is configured to control, according to the i th stored flag bit, the lower electrode plate of an i th capacitor in the second capacitor array to connect to a reference voltage or a ground voltage, such that the second comparison voltage approximates the first comparison voltage.

12. The circuit according to claim 11 , wherein at the pre-conversion stage, the second capacitor array is configured to connect the lower electrode plates of all the capacitors to the common-mode voltage, and the upper electrode plates of all the capacitors in the second capacitor array are connected to the comparator to supply the second comparison voltage for the comparator.

13. The circuit according to claim 11 , wherein the control, by the logic circuit according to an i th stored flag bit, the lower electrode plate of an i th capacitor in the second capacitor array to connect to a reference voltage or a ground voltage comprises:
if the flag bit is 1, connecting the lower electrode plate of the i th capacitor in the second capacitor array to the reference voltage;
if the flag bit is 0, connecting the lower electrode plate of the i th capacitor in the second capacitor array to the ground voltage.

14. An analog-to-digital conversion method, comprising:
at a sampling stage, connecting, by a first capacitor array, lower electrode plates of N capacitors in the first capacitor array to a first input voltage, connecting lower electrode plates of the other capacitors in the first capacitor array to a common-mode voltage, and connecting upper electrode plates of all capacitors in the first capacitor array to the common-mode voltage to sample the first input voltage, wherein N is a positive integer less than a total number of all the capacitors in the first capacitor array;
in an i th conversion at a conversion stage, controlling, by a logic circuit according to an i th stored flag bit, the lower electrode plate of an i th capacitor in the first capacitor array to connect to a reference voltage or a ground voltage, such that a first comparison voltage output by the first capacitor array approximates a second comparison voltage of a comparator, wherein i is a positive integer less than the total number of all the capacitors in the first capacitor array; and
storing, by the comparator, a comparison result between the first comparison voltage and the second comparison voltage to an i+1 th flag bit in the logic circuit, and completing analog-to-digital conversion when i+1 is equal to the total number of the capacitors in the first capacitor array.

15. The method according to claim 14 , further comprising:
at a pre-conversion stage, connecting, by the first capacitor array, the lower electrode plates of all the capacitors in the first capacitor array to the common-mode voltage, and connecting the upper electrode plates of all the capacitors in the first capacitor array to the comparator to supply the first comparison voltage for the comparator; and
storing, by the comparator, the comparison result between the first comparison voltage and the second comparison voltage to a first flag bit in the logic circuit.

16. The method according to

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Fan Shuo

Classifications

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/129 Primary

  Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title