DAC capacitor array, analog-to-digital converter, and method for reducing power consumption of analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10079609-B2
Application number	US-201715784514-A
Country	US
Kind code	B2
Filing date	Oct 16, 2017
Priority date	Oct 25, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

This disclosure discloses a DAC capacitor array, which includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) capacitor array, the DAC capacitor array being applied in an SAR analog-to-digital converter, wherein the DAC capacitor array comprises a plurality of identical sub-capacitor arrays that are connected in parallel, each of the plurality of sub-capacitor arrays comprising:
a capacitor group, comprising N capacitors that are connected in parallel, wherein N is a positive integer; and
a primary switch and a plurality of multiplexers; wherein
one terminal of each capacitor in the capacitor group connects to
an input terminal of a comparator, and connects to an input source via the primary switch; and
the other terminals of each capacitor in the capacitor group connects to a plurality of input sources via corresponding multiplexers, respectively.

2. The DAC capacitor array according to claim 1 , further comprising a symmetrical capacitor array; wherein one terminal of each capacitor in the symmetrical capacitor array is connected to the other terminal of the comparator.

3. The DAC capacitor array according to claim 1 , wherein the capacitor group comprises a significant-bit sub-capacitor group, a non-significant-bit sub-capacitor group and a supplement-bit capacitor; wherein the supplement-bit capacitor comprises a unit capacitor, the number of capacitors in the significant-bit capacitor group is P, and the number of capacitors in the non-significant-bit sub-capacitor group is M, and P and M are both a positive integer less than N and satisfy the following equation:
N=M+P+ 1.

4. The DAC capacitor array according to claim 3 , wherein the plurality of input sources comprise an analog input signal and a plurality of reference voltages, the reference voltages have a voltage value range of 0 to V R , reference voltages to which the significant-bit sub-capacitor group is connected comprise 0,

V
R

2

and V R , reference voltages to which the non-significant-bit sub-capacitor group is connected comprise

2
M

-
1

2

M
+
1

⁢

V
R

,

V
R

2

⁢

⁢
and
⁢

⁢

V
R

2

⁢

V
R

,

and V R has an adjustable value.

5. The DAC capacitor array according to claim 3 , wherein the capacitors are arranged from high to low, capacitance values of the capacitors in the significant-bit sub-capacitor group are sequentially H P , H P-1 , . . . , H 2 and H 1 , and capacitance values of the capacitors in the non-significant-bit sub-capacitor group are sequentially L M , L M-1 , . . . , L 2 and L 1 ; wherein values of H P-1 V R , H 2 V R , . . . , H 2 V R , H 1 V R ,

1

2

M
+
1

⁢

L
M

⁢

V
R

,

1

2

M
+
1

⁢

L

M
-
1

⁢

V
R

,
…
⁢

,

1

2

M
+
1

⁢

L
2

⁢

V
R

,

1

2

M
+
1

⁢

L
1

⁢

V
R

satisfy a geometric relation having an equal ration of 2.

6. A successive approximation register (SAR) analog-to-digital converter, comprising: a comparator, a register connected to an output terminal of the comparator, and a digital-to-analog converter (DAC) capacitor array connected to an input terminal of the comparator; wherein the DAC capacitor array comprises:
a plurality of identical sub-capacitor arrays that are connected in parallel, each of the plurality of sub-capacitor arrays comprises:
a capacitor group comprising N capacitors that are connected in parallel; wherein N is a positive integer; and
a primary switch and a plurality of multiplexers; wherein
one terminal of each capacitor in the capacitor group connects to an input terminal of a comparator, and connects to an input source via the primary switch; and
the other terminals of each capacitor in the capacitor group connects to a plurality of input sources via corresponding multiplexers respectively.

7. The SAR analog-to-digital converter according to claim 6 , further comprising a symmetrical capacitor array; wherein one terminal of each capacitor in the symmetrical capacitor array is connected to the other terminal of the comparator.

8. The SAR analog-to-digital converter according to claim 6 , wherein the capacitor group comprises a significant-bit sub-capacitor group, a non-significant-bit sub-capacitor group and a supplement-bit capacitor; wherein the supplement-bit capacitor comprises a unit capacitor, the number of capacitors in the significant-bit capacitor group is P, and the number of capacitors in th

Assignees

• Shenzhen Goodix Tech Co Ltd
• Shenzhen Goodix Tech Co Inc

Inventors

• Fan Shuo

Classifications

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title