DAC capacitor array, SAR analog-to-digital converter and method for reducing power consumption thereof

Patent metadata

Field	Value
Publication number	US-10270459-B2
Application number	US-201715827179-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Sep 23, 2016
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) capacitor array, comprising:
a first capacitor array and a second capacitor array, wherein each of the first capacitor array and the second capacitor array comprises:
a primary switch;
a plurality of multiplexers; and
a capacitor group, comprising a most-significant-bit capacitor, a least-significant-bit capacitor, a supplement-bit capacitor, and at least one second-most-significant-bit capacitor;
wherein one terminal of each capacitor in the first capacitor array is connected to one input terminal of a comparator and is connected to a first reference voltage via the primary switch in the first capacitor array, and the other terminal of each capacitor in the first capacitor array is connected to a plurality of input sources via a corresponding multiplexer in the first capacitor array; and
one terminal of each capacitor in the second capacitor array is connected to the other input terminal of the comparator and is connected to the first reference voltage via the primary switch in the second capacitor array, and the other terminal of each capacitor in the second capacitor array is connected to the plurality of input sources via a corresponding multiplexer in the second capacitor array; and
wherein the input sources comprise an analog input signal, the first reference voltage, a second reference voltage and a reference ground, and a difference between the second reference voltage and the reference ground is 2 times the value of the first reference voltage.

2. The DAC capacitor array according to claim 1 , wherein the least-significant-bit capacitors, the second least-significant-bit capacitors, and the most-significant-bit capacitors in the first capacitor array and the second capacitor array are arranged in the form of 2 N based on capacitances of the capacitors, N being a non-negative integer.

3. The DAC capacitor array according to claim 2 , wherein the supplement-bit capacitor and the least-significant-bit capacitor have the same capacitance.

4. A successive approximation register (SAR) analog-to-digital converter, comprising:
a comparator;
a register connected to an output terminal of the comparator; and
a digital-to-analog (DAC) capacitor array, comprising:
a first capacitor array and a second capacitor array, wherein each of the first capacitor array and the second capacitor array comprises:
a primary switch;
a plurality of multiplexers; and
a capacitor group, comprising a most-significant-bit capacitor, a lease-significant-bit capacitor, a supplement-bit capacitor, and at least one second-most-significant-bit capacitor;
wherein one terminal of each capacitor in the first capacitor array is connected to one input terminal of the comparator and is connected to a first reference voltage via the primary switch in the first capacitor array, and the other terminal of each capacitor in the first capacitor array is connected to a plurality of input sources via a corresponding multiplexer in the first capacitor array; and
one terminal of each capacitor in the second capacitor array is connected to the other input terminal of the comparator and is connected to the first reference voltage via the primary switch in the second capacitor array, and the other terminal of each capacitor in the second capacitor array is connected to the plurality of input sources via a corresponding multiplexer in the second capacitor array; and

wherein the input sources comprise an analog-input signal, the first reference voltage, a second reference voltage and a reference ground, and a difference between the second reference voltage and the reference ground is 2 times the value of the first reference voltage.

5. The SAR analog-to-digital converter according to claim 4 , wherein the least-significant-bit capacitors, the second least-significant-bit capacitors, and the most-significant-bit capacitors in the first capacitor array and the second capacitor array are arranged in the form of 2 N based on capacitances of the capacitors, N being a non-negative integer.

6. The SAR analog-to-digital converter according to claim 5 , wherein the supplement-bit capacitor and the least-significant-bit capacitor have the same capacitance.

7. The SAR analog-to-digital converter according to claim 4 , wherein the analog input signal comprises a positive-terminal analog input signal and a negative-terminal analog input signal, when in a sampling stage of the converter, the primary switch of the first capacitor array and the primary switch of the second capacitor array are turned on, the other terminal of each capacitor of the first capacitor array is connected to the positive-terminal analog input signal via the corresponding multiplexer in the first capacitor array, the other terminal of each capacitor of the second capacitor array is connected to the negative-terminal analog input signal via the corresponding multiplexer in the second capacitor array.

8. The SAR analog-to-digital converter according to claim 7 , wherein in a conversion stage of the converter, the primary switch of the first capacitor array and the primary switch of the second capacitor array are turned off, the first capacitor array is disconnected from the positive terminal analog input signal and connected to the first reference voltage via the corresponding multiplexer, a value of a most-significant bit is determined by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array.

9. The SAR analog-to-digital converter according to claim 8 , wherein the input sources connect to the other terminal of each capacitor in the first capacitor array or the second capacitor array is maintained or adjusted according to the value of the most-significant bit, and values of a second-most-significant bit and a least-significant bit are determined by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array.

10. The SAR analog-to-digital converter according to claim 9 , wherein if the output voltage of the first capacitor array is greater than the output voltage of the second capacitor array, the other terminal of each capacitor in the first capacitor array is maintained to be connected to the first reference voltage, and the other terminal of each capacitor of the second capacitor array is adjusted to be connected to a reference ground.

11. The SAR analog-to-digital converter according to claim 10 , wherein during an N th -bit conversion process: if the output voltage of the first capacitor array is greater than the output voltage of the second capacitor array, and N th -bit capacitor in the first capacitor array is connected to the first reference voltage via the corresponding multiplexer, an N th -bit capacitor in the second capacitor array is connected to the first reference voltage via the corresponding multiplexer; if the output voltage of the first capacitor array is less than the output voltage of the second capacitor array, the N th -bit capacitor of the first capacitor array is connected to a second reference voltage and the N th -bit capacitor of the second capacitor array is connected to a reference ground.

12. The SAR analog-to-digital converter according to claim 9 , wherein if the output voltage of the first capacitor array is less than the output voltage of the second capacitor array, the other terminal of each capacitor of the second capacitor array is maintained to be connected to the first reference voltage, and the other terminal of each capacitor of the first capacitor array is adjusted to be connected to a reference ground.

13. The SAR analog-to-digita

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Fan Shuo

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title