Phase-locked loop output adjustment

Patent metadata

Field	Value
Publication number	US-10411718-B2
Application number	US-201715714372-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 25, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.

First claim

What is claimed is:

1. An apparatus comprising:
a phase locked loop (PLL) circuit;
a time difference circuit coupled to an input and an output of the PLL circuit, the time difference circuit comprising:
a divider circuit connected to the output of the PLL circuit and configured to divide the output of the PLL into discrete segments; and
a phase frequency detector (PFD) connected to the divider circuit, wherein the PFD is configured to detect a time difference between edges of the discrete segments and edges of a reference signal;
a time to voltage conversion circuit coupled to an output of the time difference circuit; and

a voltage controlled delay line coupled to the output of the PLL circuit and an output of the time to voltage conversion circuit.

2. The apparatus of claim 1 , wherein the time difference circuit, the time to voltage conversion circuit, and the voltage controlled delay line are elements of a feed-forward loop.

3. The apparatus of claim 1 , wherein the time to voltage conversion circuit is coupled to the PFD and configured to convert the time difference detected by the PFD to a voltage change, and wherein the voltage controlled delay line is configured to delay the output of the PLL circuit based on the voltage change received from the time to voltage conversion circuit.

4. The apparatus of claim 1 , the time to voltage conversion circuit further comprising:
a charge pump connected to the PFD;
a switched capacitor circuit connected to the charge pump; and
a bias circuit configured to output a bias voltage based on threshold voltages of a bias PMOS transistor and a bias NMOS transistor.

5. The apparatus of claim 4 , the time to voltage conversion circuit further comprising an amplifier circuit connected to the bias circuit, the switched capacitor circuit, and the voltage controlled delay line, wherein the amplifier circuit further comprises a variable resistor and an operational amplifier.

6. The circuit of claim 5 , wherein a positive input of the operational amplifier is connected to the switched capacitor circuit, and a negative input of the operational amplifier is connected to the bias circuit and the variable resistor.

7. The circuit of claim 5 , wherein an output of the operational amplifier is connected to the voltage controlled delay line.

8. The circuit of claim 7 , wherein an amount of delay in the voltage controlled delay line is based on a magnitude of a voltage output from the amplifier circuit.

9. The circuit of claim 4 , the bias circuit further comprising:
a current source connected to a positive terminal of a bias operational amplifier, a source of the bias PMOS transistor, and a drain of the bias NMOS transistor,
wherein a gate of the bias PMOS transistor is connected to a drain of the bias PMOS transistor, and a gate of the bias NMOS transistor is connected to a drain of the bias NMOS transistor.

10. The circuit of claim 1 , wherein the reference signal comprises a reference clock signal received by the PLL circuit and the PFD.

11. The circuit of claim 1 , the voltage controlled delay line further comprising a plurality of inverters coupled in series.

12. A method comprising:
comparing an edge of a first clock signal with an edge of an output signal from a phase locked loop to detect a time difference between the edge of the first clock signal and the edge of the output signal;
converting the time difference to a voltage change, the converting comprising:
creating a bias voltage based on threshold voltages of a bias NMOS transistor and a bias PMOS transistor; and
altering the bias voltage based on an output of a charge pump to produce the voltage change; and

controlling an amount of time delay on the output signal of the phase locked loop based on the voltage change.

13. The method of claim 12 , further comprising dividing an output of the phase locked loop into a plurality of discrete segments, wherein comparing the edge of the first clock signal with the edge of the output signal from the phase locked loop comprises comparing respective edges of the first clock signal with respective edges of the plurality of discrete segments.

14. The method of claim 12 , wherein a magnitude of the voltage change is proportional to a magnitude of the time difference.

15. The method of claim 12 , wherein the threshold voltages of the bias NMOS transistor and the bias PMOS transistor are dependent on temperature.

16. The method of claim 15 , wherein the controlling the amount of time delay comprises delaying the output of the phase locked loop using a voltage controlled delay line based on the voltage change.

17. The method of claim 12 , further comprising resetting an output of the charge pump to the bias voltage after each cycle of comparing the edge of the first clock signal with the edge of the output signal from the phase locked loop.

18. The method of claim 12 , wherein the first clock signal comprises a reference clock signal received by both the phase locked loop and a phase frequency detector, wherein the phase frequency detector compares the edge of the first clock signal with the edge of the output signal from the phase locked loop.

19. The method of claim 12 , further comprising outputting the time difference between the edge of the first clock signal and the edge of the output signal as a representative signal.

20. The method of claim 19 ,
wherein the representative signal is produced on an UP line in response to the edge of the first clock signal leading the edge of the output signal from the phase locked loop; and
wherein the representative signal is produced on a DOWN line in response to the edge of the first clock signal lagging the edge of the output signal from the phase locked loop.

21. The method of claim 20 , wherein the representative signal produced on the DOWN line causes the voltage change to decrease.

22. The method of claim 20 , wherein the representative signal produced on the UP line causes the voltage change to increase.

23. The method of claim 19 , wherein the representative signal has a time length equal to the time difference between the edge of the first clock signal and the edge of the output signal.

24. The method of claim 12 , further comprising outputting a time delayed signal of the output signal.

25. The method of claim 24 , wherein the time delayed signal has a reduced time interval error.

26. An apparatus comprising:
means for comparing an edge of a first clock signal with an edge of a phase-locked loop output signal and outputting a time difference between the edges;
means for converting the time difference into a change in a voltage signal comprising:
creating a bias voltage based on threshold voltages of a bias NMOS transistor and a bias PMOS transistor; and
altering the bias voltage based on an output of a charge pump to produce the voltage signal, wherein the change in the voltage signal is proportional to the time difference; and

means for delaying the phase-locked loop output signal based on the change in the voltage signal.

Assignees

• Qualcomm Inc

Inventors

• Nagarajan Karthik
• Huang Chenling
• Bhatta Debesh

Classifications

• H03L7/235

  Nested phase locked loops · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/22

  using more than one loop · CPC title

• H03K5/1252

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title