Method and apparatus for implementing clock holdover

Patent metadata

Field	Value
Publication number	US-9660797-B2
Application number	US-201314778440-A
Country	US
Kind code	B2
Filing date	Mar 21, 2013
Priority date	Mar 21, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

The embodiments disclose a method and apparatus for implementing the clock holdover in the communication system. The apparatus receives an external source clock and outputs an output clock, and comprises a first phase-locked circuit and a second phase-locked circuit. The first phase-locked circuit is configured for taking the external source clock and a first output clock as input and outputting an intermediate clock, the first output clock is outputted by the second phase-locked circuit and fed back to the first phase-locked circuit. The first phase-locked circuit includes a first digital oscillator, and the first digital oscillator is configured to take the first output clock as a working clock to generate the intermediate clock. The second phase-locked circuit is configured for taking the intermediate clock and a local clock fed by a local oscillator as input, and outputting a second output clock.

First claim

The invention claimed is:

1. An apparatus for implementing clock holdover in a communication system, the apparatus being configured to receive an external source clock and output an output clock, the apparatus comprising:
a first phase-locked circuit configured to take the external source clock and a first output clock as input, and to output an intermediate clock, wherein the first phase-locked circuit includes a first digital oscillator configured to take the first output clock as a working clock to generate the intermediate clock; and
a second phase-locked circuit configured to take the intermediate clock and a local clock fed by a local oscillator as input, and to output the first output clock, for feeding back to the first phase-locked circuit.

2. The apparatus of claim 1 , wherein the first phase-locked circuit comprises a first phase detector (PD) for comparing a phase difference between the external source clock and the first output clock.

3. The apparatus of claim 2 , wherein the first digital oscillator is configured to process the first output clock based on the phase difference to generate the intermediate clock, such that a phase of the intermediate clock is associated with a phase of the external source clock.

4. The apparatus of claim 1 , wherein the second phase-locked circuit is an analog phase-locked circuit including a second phase detector (PD) for comparing the intermediate clock and the local clock in the second phase-locked circuit.

5. The apparatus of claim 4 , wherein the second PD is an Exclusive OR (XOR) gate.

6. The apparatus of claim 1 , wherein the apparatus further comprises a clock monitor circuit configured to monitor the external source clock, wherein the clock monitor circuit is configured to, when the external source clock is not available, control the first phase-locked circuit to maintain a constant output of the last intermediate clock generated before the external source clock is lost.

7. The apparatus of claim 1 , wherein the local oscillator is a temperature compensated crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO).

8. A communication device comprising the apparatus of claim 1 .

9. The communication device of claim 8 , wherein the communication device is a base station or a user equipment.

10. A method for implementing clock holdover in a communication system, comprising:
in a first phase-locked circuit, obtaining an external source clock, and a first output clock outputted and fed by a second phase-locked circuit, and processing the external source clock and the first output clock, by the first phase-locked circuit, to output an intermediate clock, wherein the first phase-locked circuit includes a first digital oscillator, and wherein the first digital oscillator takes the first output clock as a working clock to generate the intermediate clock; and
in the second phase-locked circuit, obtaining the intermediate clock and a local clock fed by a local oscillator, and processing the intermediate clock and the local clock, by the second phase-locked circuit, to output the first output clock for feeding to the first phase-locked circuit.

11. The method of claim 10 , wherein said processing the external source clock and the first output clock in the first phase-locked circuit to output the intermediate clock comprises comparing a phase difference between the external source clock and the first output clock.

12. The method of claim 11 , wherein said processing the external source clock and the first output clock in the first phase-locked circuit to output the intermediate clock further comprises processing the working clock based on the phase difference to generate the intermediate clock such that a phase of the intermediate clock is associated with a phase of the external source clock.

13. The method of claim 10 , wherein the second phase-locked circuit is an analog phase-locked circuit including a phase detector (PD) for comparing the intermediate clock and the local clock in the second phase-locked circuit.

14. The method of claim 10 , wherein the method further comprises monitoring the external source clock and, when the external source clock is not available, controlling the first phase-locked circuit to maintain a constant output of the last intermediate clock generated before the external source clock is lost.

15. The method of claim 10 , wherein the local oscillator is a temperature compensated crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO).

Assignees

• Ericsson Telefon Ab L M
• ERICSSON TELEFON AB L M (publ)

Inventors

• Zhu Kai

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H04J3/0688 Primary

  Change of the master or reference, e.g. take-over or failure of the master · CPC title

• H03L7/14

  for assuring constant frequency when supply or correction voltages fail · CPC title