Flip-flop including 3-state inverter

Patent metadata

Field	Value
Publication number	US-10411677-B2
Application number	US-201715649776-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Jul 14, 2016
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

First claim

What is claimed is:

1. A flip-flop comprising:
an input interface configured to receive a first signal, and output the received first signal as a second signal in synchronization with a clock;
a first latch comprising a first inverter and a second inverter, and configured to store the second signal output from the input interface in synchronization with the clock;
a third inverter configured to output the second signal stored in the first latch as a third signal in synchronization with the clock; and
a second latch comprising a fourth inverter and a fifth inverter, and configured to store the third signal output from the third inverter in synchronization with the clock,
wherein the third inverter and the fifth inverter comprise:
first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins; and
second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

2. The flip-flop of claim 1 , wherein another power contact is not disposed between the first power contact and the second power contact on the first-type fins, and
wherein another ground contact is not disposed between the first ground contact and the second ground contact on the second-type fins.

3. The flip-flop of claim 1 , wherein first, second, third, and fourth gates are disposed between the first power contact and the second power contact on the first-type fins,
wherein fifth, sixth, seventh, and eighth gates are disposed between the first ground contact and the second ground contact on the second-type fins,
wherein the first gate is connected with the fifth gate, and
wherein the fourth gate is connected with the eighth gate.

4. The flip-flop of claim 3 , wherein an output of the first latch is connected with the first gate, and
wherein an output of the fourth inverter is connected with the fourth gate.

5. The flip-flop of claim 3 , wherein the clock comprises a first clock and a second clock,
wherein the first clock is supplied to the second gate and the seventh gate, and
wherein the second clock is supplied to the third gate and the sixth gate.

6. The flip-flop of claim 3 , wherein a ninth gate is disposed adjacent to the second power contact and the second ground contact,
wherein the second power contact is located between the fourth gate and the ninth gate on the first-type fins,
wherein the second ground contact is located between the eighth gate and the ninth gate on the second-type fins, and
wherein the ninth gate forms the fourth inverter together with the first-type fins and the second-type fins.

7. The flip-flop of claim 6 , wherein a portion of the first-type fins, which is adjacent to the ninth gate and opposite to the second power contact, and a portion of the second-type fins, which is adjacent to the ninth gate and opposite to the second ground contact are connected with the eighth gate.

8. The flip-flop of claim 3 , further comprising:
a sixth inverter configured to invert the third signal and output the inverted third signal as a fourth signal,
wherein a ninth gate is disposed adjacent to the second power contact and the second ground contact,
wherein the second power contact is located between the fourth gate and the ninth gate on the first-type fins,
wherein the second ground contact is located between the eighth gate and the ninth gate on the second-type fins, and
wherein the ninth gate forms the sixth inverter together with the first-type fins and the second-type fins.

9. The flip-flop of claim 3 , wherein ninth and tenth gates are disposed adjacent to the second power contact and the second ground contact,
wherein the second power contact is located between the fourth gate and the ninth gate on the first-type fins,
wherein the second ground contact is located between the eighth gate and the ninth gate on the second-type fins,
wherein a reset signal is supplied to the tenth gate,
wherein an output of the third inverter is supplied to the ninth gate,
wherein the first-type fins of a side of the tenth gate are connected with the eighth gate,
wherein a third ground contact supplied with a ground voltage is disposed on the second-type fins of the side of the tenth gate, and
wherein the second-type fins between the ninth gate and the tenth gate are connected with the eighth gate.

10. The flip-flop of claim 3 , wherein ninth and tenth gates are disposed adjacent to the second power contact and the second ground contact,
wherein the second power contact is located between the fourth gate and the ninth gate on the first-type fins,
wherein the second ground contact is located between the eighth gate and the ninth gate on the second-type fins,
wherein a set signal is supplied to the ninth gate,
wherein an output of the third inverter is supplied to the tenth gate,
wherein a third power contact supplied with a power supply voltage is disposed on the first-type fins of a side of the tenth gate,
wherein the second-type fins of the side of the tenth gate are connected with the eighth gate, and
wherein the first-type fins between the ninth gate and the tenth gate are connected with the eighth gate.

11. The flip-flop of claim 1 , wherein first, second, third, fourth, and fifth gates are disposed between the first power contact and the second power contact,
wherein sixth, seventh, eighth, ninth, and tenth gates are disposed between the first ground contact and the second ground contact,
wherein the first gate is connected with the sixth gate,
wherein the fifth gate is connected with the tenth gate,
wherein an output of the first latch is connected with the first gate,
wherein an output of the fourth inverter is connected with the fifth gate,
wherein the clock comprises a first clock and a second clock,
wherein the first clock is supplied to the second gate and the ninth gate, and
wherein the second clock is supplied to the third gate and the eighth gate.

12. The flip-flop of claim 11 , wherein a first jumper, which electrically connects the first-type fins separated by the fourth gate, is disposed over the fourth gate, and
wherein a second jumper, which electrically connects the second-type fins separated by the seventh gate, is disposed over the seventh gates.

13. The flip-flop of claim 11 , wherein the third gate and the ninth gate are connected to each other.

14. The flip-flop of claim 1 , wherein a power supply voltage of at least one of the first power contact and the second power contact and a ground voltage of at least one of the first ground contact and the second ground contact are shared with another element.

15. The flip-flop of claim 1 , wherein the input interface comprises a sixth inverter configured to output the second signal in synchronization with the clock,
wherein the second inverter and the sixth inverter comprise:
third transistors of the first type formed between a third power contact and a fourth power contact supplied with the power supply voltage on the first-type fins; and
fourth transistors of the second type formed between a third ground contact and a fourth ground contact supplied with the ground voltage on the second-type fins.

16. The flip-flop of claim 15 , wherein first, second, third, and fourth gates are disposed between the third power contact and the fourth power contact on the first-type fins,
wherein fifth, sixth, seventh, and eighth gates are disposed between the third ground contact and the fourth ground contact on the second-type fin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Lee Dalhee
• Oh Hyoung-Suk
• Lee keunho
• Song Taejoong
• Cho Sungwe

Classifications

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title

• H03K23/001

  using elements not covered by groups H03K23/002 and H03K23/74 - H03K23/84 · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title