Encapsulated nanostructures and devices containing encapsulated nanostructures

Patent metadata

Field	Value
Publication number	US-10411096-B2
Application number	US-201815966482-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Oct 30, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.

First claim

We claim:

1. A device comprising:
a substrate, and
a nanostructure, the nanostructure comprising:
a fin structure disposed on the substrate, the fin structure having a fin axis, wherein the fin structure comprises:
at least one silicon nanowire having a long axis extending along the fin axis, the at least one silicon nanowire comprising monocrystalline silicon; and
a matrix material surrounding the nanowire, the matrix material comprising a monocrystalline silicon:germanium alloy (SiGe),

wherein the at least one silicon nanowire has a first dimension extending less than 50 nm along a first direction perpendicular to the fin axis, and a second dimension extending less than 50 nm along a second direction perpendicular to the first direction and the fin axis,
wherein the fin structure has an outer surface comprising SiGe material,
wherein the at least one silicon nanowire does not extend on the outer surface of the fin structure, and
wherein the at least one silicon nanowire and silicon:germanium alloy (SiGe) comprise a unitary monocrystalline structure.

2. The device of claim 1 , wherein the silicon:germanium alloy (SiGe) comprises a germanium concentration of greater than 50%.

3. The device of claim 1 , wherein the at least one silicon nanowire is a strained silicon nanowire.

4. The device of claim 1 , wherein the fin axis extends parallel to a plane of the substrate,
wherein the at least one silicon nanowire has a first dimension extending less than 20 nm along a first direction perpendicular to the fin axis, and a second dimension extending less than 20 nm along a second direction perpendicular to the first direction and the fin axis.

5. A nanostructure, comprising a fin structure disposed on a substrate, the fin structure comprising:
(a) at least one silicon nanowire allowing for a current flow in the fin structure, the nanowire comprising monocrystalline silicon; and
(b) a matrix material surrounding the nanowire, the matrix material comprising a monocrystalline silicon:germanium alloy (SiGe);
wherein the fin structure is elongated in a first direction that defines the direction of current flow in the fin structure and a cross section having dimensions on the order of 50 nm or less;
wherein the at least one silicon nanowire does not extend on the outer surface of the fin structure; and
wherein the at least one silicon nanowire and silicon:germanium alloy (SiGe) comprise a unitary monocrystalline structure.

6. The nanostructure of claim 5 , wherein the silicon:germanium alloy (SiGe) comprises a germanium concentration of greater than 50%.

7. The nanostructure of claim 5 , wherein the at least one silicon nanowire is a strained silicon nanowire.

8. The nanostructure of claim 5 , wherein the at least one silicon nanowire comprises a plurality of silicon nanowires, wherein the matrix material surrounds the plurality of silicon nanowires.

9. The nanostructure of claim 5 , wherein the first direction extends parallel to a plane of the substrate, wherein the cross section is on the order of 20 nm or less.

10. The nanostructure of claim 5 , wherein the at least one silicon nanowire is defect-free.

11. The nanostructure according to claim 5 , wherein the cross section is on the order of 10 nm or less.

12. A device comprising:
(a) a substrate;
(b) a first sidewall structure and a second sidewall structure disposed on the substrate; and
(c) a nanostructure according to claim 6 disposed on the substrate between the first sidewall structure and the second sidewall structure.

13. The device according to claim 12 , wherein the silicon:germanium alloy (SiGe) comprises a germanium concentration of greater than 50%.

14. The device according to claim 12 , wherein the at least one silicon nanowire comprises a plurality of silicon nanowires, wherein the matrix material surrounds the plurality of silicon nanowires.

15. The device according to claim 12 , wherein the first direction extends parallel to a plane of the substrate, wherein the cross section is on the order of 20 nm or less.

16. The device according to claim 12 , wherein a portion of the matrix material surrounding the nanowire is removed to form a freestanding nanowire portion.

17. The device according to claim 16 , wherein the freestanding nanowire portion is surrounded by a gate material.

Assignees

• Univ Florida
• Varian Semiconductor Equipment Ass Inc

Inventors

• Hatem Christopher
• Jones Kevin S
• Brewer William M

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title