Nanowire capacitor for bidirectional operation

Patent metadata

Field	Value
Publication number	US-9035383-B2
Application number	US-201313967807-A
Country	US
Kind code	B2
Filing date	Aug 15, 2013
Priority date	Jan 28, 2013
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A method of fabricating an electronic device includes the following steps. At least one first set and at least one second set of nanowires and pads are etched in an SOI layer of an SOI wafer. A first gate stack is formed that surrounds at least a portion of each of the first set of nanowires that serves as a channel region of a capacitor device. A second gate stack is formed that surrounds at least a portion of each of the second set of nanowires that serves as a channel region of a FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device that extends at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

First claim

What is claimed is:

1. An electronic device, comprising:
at least one first set of nanowires and first set of pads etched in an SOI layer of an SOI wafer and at least one second set of nanowires and second set of pads etched in the SOI layer, wherein the first set of pads are attached at opposite ends of the at least one first set of nanowires in a ladder-like configuration, wherein the second set of pads are attached at opposite ends of the at least one second set of nanowires in another ladder-like configuration, and wherein the at least one first set of nanowires and the first set of pads correspond to a capacitor device and the at least one second set of nanowires and the second set of pads correspond to a FET device, the capacitor device and the FET device both being present on the SOI wafer;
a first gate stack that surrounds at least a portion of each of the at least one first set of nanowires that serves as a channel region of the capacitor device, wherein portions of the at least one first set of nanowires extending out from the first gate stack and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are undoped;
a second gate stack that surrounds at least a portion of each of the at least one second set of nanowires that serves as a channel region of the FET device, wherein portions of the at least one second set of nanowires extending out from the second gate stack and the second set of pads serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped;
first spacers on opposite sides of the first gate stack and second spacers on opposite sides of the second gate stack, wherein the first spacers have a width wa and the second spacers have a width wb, and wherein wa<wb;
a first silicide formed on the source and drain regions of the capacitor device; and
a second silicide formed on the source and drain regions of the FET device,
wherein an amount of the first silicide formed on the source and drain regions of the capacitor device is greater than an amount of the second silicide formed on the source and drain regions of the FET device such that first silicide formed on the source and drain regions of the capacitor device extends at least to an edge of the first gate stack while the second silicide formed on the source and drain regions of the FET device remains within the source and drain regions of the FET device.

2. The electronic device of claim 1 , wherein the channel region of the capacitor device is undoped, and wherein the first silicide extends at least to the edge of the first gate stack forming a Schottky junction between the first silicide and the channel region of the capacitor device which is undoped.

3. The electronic device of claim 1 , wherein the channel region of the capacitor device is undoped, and wherein the first silicide extends beyond the edge of the first gate stack into the channel region of the capacitor device and thus the first silicide is present under the first gate stack.

4. The electronic device of claim 1 , further comprising:
epitaxial silicon present only on the source and drain regions of the FET device.

5. An electronic device, comprising:
at least one first set of nanowires and first set of pads in a SOI layer of an SOI wafer and at least one second set of nanowires and second set of pads etched in the SOI layer, wherein the first set of pads are attached at opposite ends of the at least one first set of nanowires in a ladder-like configuration, wherein the second set of pads are attached at opposite ends of the at least one second set of nanowires in another ladder-like configuration, and wherein the at least one first set of nanowires and the first set of pads correspond to a capacitor device and the at least one second set of nanowires and the second set of pads correspond to a FET device, the capacitor device and the FET device both being present on the SOI wafer;
a first gate stack that surrounds at least a portion of each of the at least one first set of nanowires that serves as a channel region of the capacitor device, wherein portions of the at least one first set of nanowires extending out from the first gate stack and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are doped;
a second gate stack that surrounds at least a portion of each of the at least one second set of nanowires that serves as a channel region of the FET device, wherein portions of the at least one second set of nanowires extending out from the second gate stack and the second set of pads serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped;
first spacers on opposite sides of the first gate stack and second spacers on opposite sides of the second gate stack, wherein the first spacers have a width wa and the second spacers have a width wb, and wherein wa<wb;
a first silicide on the source and drain regions of the capacitor device; and
a second silicide on the source and drain regions of the FET device,
wherein an amount of the first silicide formed on the source and drain regions of the capacitor device is greater than an amount of the second silicide formed on the source and drain regions of the FET device such that first silicide formed on the source and drain regions of the capacitor device extends into the channel region of the capacitor device which is undoped while the second silicide formed on the source and drain regions of the FET device remains within the source and drain regions of the FET device.

6. The electronic device of claim 2 , wherein the first silicide extends beyond a junction between the source and drain regions of the capacitor device which are doped and the channel region of the capacitor device which is undoped forming a Schottky junction between the first silicide and the channel region of the capacitor device.

7. The electronic device of claim 2 , further comprising:
epitaxial silicon present only on the source and drain regions of the FET device.

Assignees

• IBM

Inventors

• Bangsaruntip Sarunya
• Majumdar Amlan
• Sleight Jeffrey W

Classifications

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• Y10S977/762

  Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D30/0212

  using self-aligned silicidation · CPC title