Thermal and electromagnetic interference shielding for die embedded in package substrate

Patent metadata

Field	Value
Publication number	US-10410971-B2
Application number	US-201715689967-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Aug 29, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.

First claim

What is claimed is:

1. A package, comprising:
a package substrate including a first cavity;
an integrated device including a first active side and an inactive side, and embedded in the first cavity; and
a structure partially enclosing the integrated device, the structure including a first layer in the first cavity and a second layer,
wherein the first layer is coupled between the package substrate and the integrated device, and
wherein the second layer is disposed over the inactive side of the integrated device.

2. The package of claim 1 , wherein the first layer and the second layer include a conductive material.

3. The package of claim 2 , wherein at least one of the first layer and the second layer is coupled to an electrical ground or a chassis ground.

4. The package of claim 2 , wherein the conductive material includes one or more of a copper material or a conductive polymer.

5. The package of claim 1 , wherein the integrated device comprises:
a die having a second active side and the inactive side;
a plurality of conductive pillars electrically coupled to elements on the second active side of the die and extending perpendicular therefrom; and
a layer of dielectric material disposed over the second active side of the die and coupled to the plurality of conductive pillars.

6. The package of claim 1 , wherein the second layer extends over a first surface of the package substrate, wherein the first surface is outside of the first cavity.

7. The package of claim 1 , wherein the first layer is coupled to the second layer.

8. The package of claim 1 , wherein the integrated device is embedded in the first cavity such that a gap exists between at least (i) a first side of the integrated device and a corresponding first side of the first cavity and (ii) a second side of the integrated device and a corresponding second side of the first cavity.

9. The package of claim 1 , wherein the package substrate includes a prepreg substrate printed circuit board (PCB).

10. The package of claim 1 , further comprising:
a second cavity in at least a first side and a second side of the first cavity; and
a third layer of conductive material contained within the second cavity.

11. The package of claim 10 , wherein the third layer of conductive material is coupled to the first layer.

12. The package of claim 1 , further comprising a redistribution layer (RDL) coupled to the first active side of the integrated device.

13. The package of claim 12 , wherein the first layer is coupled to at least one of an electrical ground and a chassis ground via a conductive line in the RDL.

14. The package of claim 1 , wherein the package substrate further includes a plurality of vias.

15. A package, comprising:
a package substrate including a first cavity and a second cavity;
an integrated device including an active side and an inactive side, and embedded in the first cavity; and
a structure partially enclosing the integrated device, the structure including a first layer, a second layer, and a third layer,
wherein the first layer is coupled between the package substrate and the integrated device,
wherein the second layer is disposed over the inactive side of the integrated device, and
wherein the third layer is embedded in the second cavity.

16. The package of claim 15 , wherein the package substrate includes a prepreg substrate printed circuit board (PCB).

17. The package of claim 15 , wherein the third layer is coupled to the first layer.

18. The package of claim 15 , further comprising a redistribution layer (RDL) coupled to the active side of the integrated device.

19. The package of claim 15 , wherein the first layer, the second layer, and the third layer are electrically coupled to at least one of an electrical ground and a chassis ground.

20. A package, comprising:
a package substrate including at least a first cavity;
an integrated device including a first active side and an inactive side, and embedded in the first cavity;
a structure partially enclosing the integrated device, the structure including at least a first layer in the first cavity and a second layer,
wherein the first layer is coupled between the package substrate and the integrated device, and
wherein the second layer is disposed over the inactive side of the integrated device; and
a layer of insulating material disposed between the structure and the integrated device.

21. The package of claim 20 , wherein the integrated device comprises:
a die having a second active side and the inactive side;
a plurality of conductive pillars electrically coupled to elements on the second active side of the die and extending perpendicular therefrom; and
a layer of dielectric material disposed over the second active side and coupled to the plurality of conductive pillars, wherein the layer of insulating material is disposed over one or more of the inactive side the plurality of conductive pillars, or the layer of dielectric material.

22. The package of claim 20 , wherein the package substrate further comprises a second cavity, and wherein the structure further comprises a third layer contained within the second cavity.

23. The package of claim 22 , wherein the third layer is coupled to the first layer.

24. The package of claim 20 , further comprising a redistribution layer (RDL) coupled to the first active side of the integrated device.

25. The package of claim 24 , wherein the first layer is coupled to at least one of an electrical ground and a chassis ground via a conductive line in the RDL.

26. A method of fabricating a package, the method comprising:
forming a first cavity in a package substrate;
depositing an integrated device into the first cavity, the integrated device having an active side and an inactive side; and
disposing a first layer of conductive material in the first cavity about the integrated device and a second layer of conductive material about the integrated device such that the integrated device is partially enclosed in the conductive material,
wherein the first layer of conductive material is coupled between the package substrate and the integrated device, and
wherein the second layer of conductive material is disposed over the inactive side of the integrated device.

27. The method of claim 26 , wherein depositing the integrated device into the first cavity further comprises positioning the integrated device in the first cavity such that a gap exists between at least (i) a first side of the integrated device and a corresponding first side of the first cavity and (ii) a second side of the integrated device and a corresponding second side of the first cavity.

28. The method of claim 27 , wherein disposing the first layer of conductive material and the second layer of conductive material about the integrated device further comprises:
depositing a first seed layer over (i) the first side of the integrated device and the corresponding side of the first cavity and (ii) a second side of the integrated device and the corresponding side of the first cavity;
depositing a second seed layer over the inactive side of the integrated device;
forming the first layer of conductive material utilizing the first seed layer; and
forming the second layer of conductive material utilizing the second seed layer.

29. The method of claim 28 , wherein the first seed layer and

Assignees

• Qualcomm Inc

Inventors

• Rae David Fraser
• We Hong Bok
• Healy Christopher
• Kim Chin-Kwan

Classifications

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title