Method and device for reducing contamination for reliable bond pads

Patent metadata

Field	Value
Publication number	US-10410854-B2
Application number	US-201715857546-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

First claim

The invention claimed is:

1. A method for processing a semiconductor wafer, comprising:
providing the semiconductor wafer that includes an active surface on a frontside of the semiconductor wafer and an inactive surface on a backside of the semiconductor wafer, wherein the active and inactive surfaces are opposite surfaces of the semiconductor wafer, and the active surface is a surface on which transistors are formed;
forming front-end-of-line layers on the active surface and the inactive surface of the semiconductor wafer, wherein the front-end-of-line layers include one or more gate layers disposed on the active surface and the inactive surface of the semiconductor wafer, and the front-end-of-line layers further include one or more front-end-of-line dielectric layers disposed on the one or more gate layers on the active surface and the inactive surface;
patterning the one or more gate layers on the active surface of the semiconductor wafer to form gates of the transistors;
after patterning the one or more gate layers on the active surface of the semiconductor wafer to form the gates of the transistors, forming a back-end-of-line dielectric layer over the transistors, wherein the back-end-of-line dielectric layer includes a bond pad;
after forming the back-end-of-line dielectric layer, forming a deep trench penetrating into the back-end-of-line dielectric layer with a deep trench etching process that deposits a polymer residue on the one or more front-end-of-line dielectric layers on the inactive surface of the semiconductor wafer; and
after forming the deep trench, performing a cleaning process on the backside of the semiconductor wafer, wherein the cleaning process removes the polymer residue and at least a portion of the one or more front-end-of-line dielectric layers from the inactive surface.

2. The method of claim 1 wherein the bond pad comprises aluminum.

3. The method of claim 1 wherein the one or more front-end-of-line dielectric layers comprise a spacer stack that includes a nitride layer.

4. The method of claim 3 wherein the spacer stack further includes an oxide layer disposed below the nitride layer.

5. The method of claim 1 wherein the cleaning process includes a wet cleaning process that uses a cleaning solution to remove the portion of the one or more front-end-of-line dielectric layers from the inactive surface.

6. The method of claim 5 wherein the cleaning solution is a hydrogen fluoride solution, and the portion of the one or more front-end-of-line dielectric layers is a portion of a nitride layer.

7. The method of claim 1 wherein the cleaning process includes a dry cleaning process that removes the portion of the one or more front-end-of-line dielectric layers from the inactive surface at a bevel region of the semiconductor wafer, and the dry cleaning process exposes the one or more gate layers on the inactive surface of the semiconductor wafer.

8. The method of claim 1 wherein the cleaning process includes a dry cleaning process that removes the portion of the one or more front-end-of-line dielectric layers from the inactive surface at a bevel region of the semiconductor wafer, and the dry cleaning process removes at least a portion of the one or more gate layers from the inactive surface of the semiconductor wafer.

9. The method of claim 1 wherein the cleaning process includes a wet cleaning process that uses a cleaning solution to completely remove the one or more front-end-of-line dielectric layers from the inactive surface and expose the one or more gate layers on the inactive surface.

10. The method of claim 4 wherein the cleaning process includes a wet cleaning process that uses a cleaning solution to completely remove the one or more front-end-of-line dielectric layers from the inactive surface and expose the one or more gate layers on the inactive surface.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Mou Honghui
• Li Xiaodong
• Tan Yun Ling
• See Alex
• Li Liang

Classifications

• H10P70/234 Primary

  the processing being the formation of vias or contact holes · CPC title

• H10P70/56

  Cleaning of wafer backside · CPC title

• H10P70/18

  by combined dry cleaning and wet cleaning (H10P70/52 takes precedence) · CPC title

• H10W72/07211

  Treating the bond pad before connecting, e.g. by applying flux or cleaning · CPC title

• H10W10/01

  Manufacture or treatment · CPC title