Sense flags in a memory device

Patent metadata

Field	Value
Publication number	US-10409506-B2
Application number	US-201816117348-A
Country	US
Kind code	B2
Filing date	Aug 30, 2018
Priority date	Nov 9, 2010
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

First claim

What is claimed is:

1. A method for programming sense flags, the method comprising:
programming memory cells coupled to a first plurality of data lines in a main memory array while each data line of the first plurality of data lines is connected to sensing circuitry, each data line of a second plurality of data lines in the main memory array are disconnected from the sensing circuitry, and each data line of a third plurality of data lines in a flag memory array are connected to the sensing circuitry; and
programming memory cells coupled to the second plurality of data lines while programming memory cells coupled to the third plurality of data lines with flag data indicative of the memory cells coupled to the second plurality of data lines being programmed while each data line of the first plurality of data lines is disconnected from the sensing circuitry, while each data line of the second plurality of data lines is connected to the sensing circuitry, and while each data line of the third plurality of data lines is connected to the sensing circuitry.

2. The method of claim 1 , further comprising loading user data into a dynamic data cache coupled to the first plurality of data lines prior to programming the memory cells coupled to the first plurality of data lines.

3. The method of claim 2 , wherein programming the memory cells coupled to the first plurality of data lines in the main memory array comprises programming the memory cells coupled to the first plurality of data lines in the main memory array with the user data loaded into the dynamic data cache.

4. The method of claim 2 , wherein the flag memory array is a first flag memory array, the method further comprising loading other flag data into a portion of the dynamic data cache coupled to a fourth plurality of data lines in a second flag memory array while loading the user data into the dynamic data cache.

5. The method of claim 1 , wherein programming the memory cells coupled to the third plurality of data lines in the flag memory array comprises programming data that includes both the flag data and other data associated with a particular page of data of the main memory array.

6. The method of claim 1 , wherein the flag data comprises a plurality of bytes of data.

7. The method of claim 6 , wherein the plurality of bytes of data comprises a bit indicative of the memory cells coupled to the second plurality of data lines being programmed that is to be read concurrently with memory cells coupled to the first plurality of data lines.

8. The method of claim 7 , wherein programming the memory cells coupled to the third plurality of data lines in the flag memory array comprises programming the bit indicative of the memory cells coupled to the second plurality of data lines being programmed to a memory cell coupled to a particular data line of the third plurality of data lines in the flag memory array.

9. The method of claim 1 , wherein a first data line of the first plurality of data lines in the main memory array and a second data line of the second plurality of data lines in the main memory array are adjacent first and second data lines.

10. The method of claim 9 , wherein a read gate voltage of the memory cell coupled to the first data line of the adjacent first and second data lines is to be adjusted in response to the flag data indicative of the memory cell coupled to the second data line of the adjacent first and second data lines being programmed.

11. The method of claim 1 , wherein programming the memory cells coupled to the first plurality of data lines in the main memory array comprises programming memory cells of a first page of memory cells, and wherein programming the memory cells coupled to the second plurality of data lines in the main memory array comprises programming memory cells of a second page of memory cells adjacent the first page of memory cells.

12. The method of claim 11 , wherein programming the memory cells of the first page of memory cells comprises programming memory cells of an even page of memory cells, and wherein programming the memory cells of the second page of memory cells adjacent the first page of memory cells comprises programming memory cells of an odd page of memory cells.

13. A method for sensing flags, the method comprising:
performing a sense operation on memory cells coupled to a first plurality of data lines of a main memory array and memory cells coupled to data lines of a flag memory array; and
determining a program indication of memory cells coupled to a second plurality of data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array;
wherein the first plurality of data lines and the second plurality of data lines are mutually exclusive.

14. The method of claim 13 and further comprising:
adjusting read gate voltages for a state of the memory cells coupled to the first plurality of data lines of the main memory array when the program indication indicates that the memory cells coupled to the second plurality of data lines of the main memory array are not programmed.

15. The method of claim 13 and further comprising:
determining states of the memory cells coupled to the first plurality of data lines of the main memory array without adjustment of read gate voltages when the program indication indicates that the memory cells coupled to the second plurality of data lines of the main memory array are programmed.

16. The method of claim 13 and further comprising:
performing a sense operation on a lower page of the memory cells coupled to the first plurality of data lines responsive to the program indication.

17. The method of claim 13 and further comprising:
adjusting read gate voltages for a state of the memory cells coupled to the first plurality of data lines of the main memory array when the program indication indicates that the memory cells coupled to the second plurality of data lines of the main memory array are programmed.

18. The method of claim 13 and further comprising:
determining states of the memory cells coupled to the first plurality of data lines of the main memory array without adjustment of read gate voltage when the program indication indicates that the memory cells coupled to the second plurality of data lines of the main memory array are not programmed.

19. The method of claim 13 , wherein performing the sense operation on the memory cells coupled to the first plurality of data lines of the main memory array comprises performing the sense operation on memory cells coupled to every other data line of the main memory array.

20. The method of claim 19 , wherein determining the program indication of the memory cells coupled to the second plurality of data lines of the main memory array comprises determining a program indication of memory cells coupled to every other data line of the main memory array.

Assignees

• Micron Technology Inc

Inventors

• Ahmed Shafqat
• Hasnat Khaled
• Kalavade Pranav
• Parat Krishna
• Yip Aaron
• Helm Mark A
• Bicksler Andrew

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title