Method for processing a semiconductor workpiece and semiconductor device

Patent metadata

Field	Value
Publication number	US-10403725-B2
Application number	US-201815925914-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 21, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A method for processing a semiconductor workpiece, including: forming a trench structure in a first region of a semiconductor workpiece, extending from a surface of the semiconductor workpiece to a first depth, forming at least one recess in a second region of the semiconductor workpiece laterally next to the first region, the recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece to a second depth less than the first depth; forming a material layer over the semiconductor workpiece, the material layer filling the trench structure and recess and covering the surface of the semiconductor workpiece in the first region and in the second region; and planarizing the semiconductor workpiece to partially remove the material layer in the first region and in the second region, wherein the material layer remains in the trench structure and in the at least one recess.

First claim

What is claimed is:

1. A method for processing a semiconductor workpiece, the method comprising:
forming a trench structure in a power device region of a semiconductor workpiece, the trench structure extending from a surface of the semiconductor workpiece into the semiconductor workpiece to a first depth,
forming at least one recess in a functional region of the semiconductor workpiece laterally next to the power device region, the at least one recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece to a second depth less than the first depth, wherein the at least one recess comprises a width greater than the second depth;
forming at least one material layer over the semiconductor workpiece, wherein the at least one material layer comprises a semiconductor material, to fill the trench structure and the at least one recess and to cover the surface of the semiconductor workpiece in the power device region and in the functional region;
planarizing the semiconductor workpiece to partially remove the at least one material layer in the power device region and in the functional region, wherein first portions of the at least one material layer remain in the trench structure and a second portion of the at least one material layer remains in the recess;
forming a power device structure in the power device region, wherein the first portions of the at least one material layer are part of the power device structure; and
forming a functional structure in the functional region, wherein the second portion of the at least one material layer is part of the functional structure.

2. The method according to claim 1 ,
wherein forming the trench structure comprises forming a plurality of trenches laterally next to each other.

3. The method according to claim 1 ,
wherein the least one recess and the trench structure are formed during at least one common processing stage.

4. The method according to claim 2 ,
wherein each trench of the plurality of trenches is formed to have the first depth and a width, wherein the respective width of the respective trench of the plurality of trenches is less than the width of the at least one recess.

5. The method according to claim 1 , further comprising:
forming a first insulating layer in the power device region of the semiconductor workpiece to separate the first portions of the at least one material layer remaining in the trench structure from a first portion of the semiconductor workpiece below the first insulating layer.

6. The method according to claim 5 , further comprising:
forming a second insulating layer in the functional region of the semiconductor workpiece to separate the second portion of the at least one material layer remaining in the at least one recess from a second portion of the semiconductor workpiece below the second insulating layer.

7. The method according to claim 5 ,
wherein the first portion of the semiconductor workpiece comprises a semiconductor material, or
wherein the second portion of the semiconductor workpiece comprises a semiconductor material.

8. The method according to claim 1 ,
wherein the power device structure comprises a field-effect transistor structure and
wherein the first portions of the at least one material layer remaining in the trench structure are part of a gate structure of the field-effect transistor structure.

9. The method according to claim 1 ,
wherein the power device region is a vertical device region and wherein the first portions of the at least one material layer remaining in the trench structure are part of a vertical semiconductor structure.

10. The method according to claim 9 ,
wherein the vertical semiconductor structure comprises a vertical diode structure, a vertical transistor structure, or a vertical thyristor structure.

11. The method according to claim 1 ,
wherein the functional region is at least one of a sensor region or a protection region, and
wherein the second portion of the at least one material layer remaining in the at least one recess is part of at least one of a sensor structure or a protection structure.

12. The method according to claim 1 ,
wherein the functional region is an edge-termination region for the power device region and wherein the second portion of the at least one material layer remaining in the at least one recess is part of an edge-termination structure.

13. The method according to claim 1 ,
wherein the functional region is a lateral device region, and
wherein the second portion of the at least one material layer remaining in the at least one recess is part of a lateral semiconductor structure.

14. The method according to claim 13 ,
wherein the lateral semiconductor structure comprises at least one of the following lateral semiconductor structures:
a lateral diode structure,
a lateral transistor structure,
a lateral thyristor structure, or
a lateral resistor structure.

15. The method according to claim 1 ,
wherein the at least one recess comprises a plurality of recesses, wherein each of the recesses may be part of one or more of the following structures:
an edge-termination structure,
a sensor structure, or
a lateral device.

16. The method according to claim 1 ,
wherein the first portions of the at least one material layer remaining in the trench structure comprise a semiconductor material doped with a first dopant type and a first dopant concentration; and
wherein the second portion of the at least one material layer remaining in the at least one recess comprises a semiconductor material doped with a second dopant type and a second dopant concentration.

17. A semiconductor device, comprising:
a trench structure in a power device region of a semiconductor workpiece, the trench structure comprising a plurality of trenches, each trench of the plurality of trenches extending from a surface of the semiconductor workpiece into the semiconductor workpiece to a first depth and having a first width,
at least one recess in a functional region of the semiconductor workpiece laterally next to the power device region, the at least one recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece with a second depth less than the first depth and with a second width greater than the first width, wherein the second width of the at least one recess is greater than the second depth; and
a plurality of material layer portions comprising a semiconductor material, wherein a respective first material portion of the plurality of material layer portions is disposed in a respective trench of the plurality of trenches that is part of a power device structure, wherein a second material portion of the plurality of material layer portions is disposed in the at least one recess that is part of a functional structure, and wherein a portion of the surface laterally outside of the plurality of trenches and of the at least one recess is free from the plurality of material layer portions.

18. The semiconductor device according to claim 17 ,
wherein the functional region is at least one of a sensor region or a protection region, and
wherein the second material layer portion disposed in the at least one recess is part of at least one of a sensor structure or a protection structure.

19. The semiconductor device according to claim 17 ,
wherein the functional region is a lateral device region, and
wherein the second material layer portion disposed in the at least one recess is part of a lateral semiconductor structure.

Assignees

• Infineon Technologies Ag

Inventors

• Karmous Alim

Classifications

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10P72/00

  Handling or holding of wafers, substrates or devices during manufacture or treatment thereof · CPC title

• H10P95/00 Primary

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H01L29/7815

  Electricity · mapped topic

• H01L29/7455

  Electricity · mapped topic