Method for fabricating electronic package

Patent metadata

Field	Value
Publication number	US-10403570-B2
Application number	US-201816157430-A
Country	US
Kind code	B2
Filing date	Oct 11, 2018
Priority date	May 18, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

First claim

What is claimed is:

1. A method for fabricating an electronic package, comprising:
providing a circuit structure having a first surface provided with a first circuit layer and an opposite second surface provided with a second circuit layer;
disposing on the second surface of the circuit structure a plurality of conductive posts electrically connected to the second circuit layer;
forming on the second surface of the circuit structure an insulating layer encapsulating the conductive posts;
forming on the first surface of the circuit structure a metal layer electrically connected to the first circuit layer;
disposing on the first surface of the circuit structure an electronic element electrically connected to the metal layer;
forming on the first surface of the circuit structure an encapsulant encapsulating the electronic element; and
removing a portion of the insulating layer to expose a portion of a surface of each of the conductive posts.

2. The method of claim 1 , wherein the first circuit layer has a minimum trace width less than a minimum trace width of the second circuit layer.

3. The method of claim 1 , wherein the metal layer is a patterned circuit layer.

4. The method of claim 1 , wherein the encapsulant and the insulating layer are made of the same material.

5. The method of claim 1 , wherein the encapsulant and the insulating layer are made of different materials.

6. The method of claim 1 , wherein the encapsulant extends to a side surface of the circuit structure.

7. The method of claim 1 , wherein the encapsulant is in contact with the insulating layer.

8. The method of claim 1 , further comprising disposing a plurality of conductive elements on the conductive posts.

9. The method of claim 1 , further comprising disposing an electronic component on the conductive posts.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Li Hung-Yuan
• Lai Chieh-Lung
• Peng Shih-Liang
• Lu Chang-Lun

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/0198

  batch processes · CPC title