Semiconductor integrated circuit and semiconductor integrated circuit diagnosis method

Patent metadata

Field	Value
Publication number	US-10401430-B2
Application number	US-201715691121-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Mar 21, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a plurality of scan chains each including a retention flip-flop; and
a diagnosis circuit configured to perform restoration of data saved in a retention section of the retention flip-flop by reading the data from the retention section, and after the restoration of the data, perform diagnosis of the retention flip-flop by performing comparison to determine whether or not a first value of a first output data string obtained as a result of a scan shift in each of the plurality of scan chains before the save of the data in the retention section and a second value of a second output data string obtained as a result of a scan shift of the data in each of the plurality of scan chains after the restoration of the data agree with each other, wherein the data is “0” or “1”;
a switching circuit configured to perform switching of inputs to each of the plurality of scan chains to the “0” or “1” is provided;
the first value is an expected value of the first output data string obtained as a result of a scan shift of the “0” or “1” in the plurality of scan chains after setting of the “0” or “1” in the inputs to the plurality of scan chains via the switching circuit;
the second value is a value of the second output data string obtained as a result of input of the data read and restored from the retention section to the plurality of scan chains and a scan shift of the data, and
after the diagnosis circuit performs diagnosis of the retention flip-flop by performing comparison to determine whether or not the first value and the second value when the inputs to the plurality of scan chains are fixed to one of the “0” and the “1” by the switching circuit agree with each other, the diagnosis circuit performs diagnosis of the retention flip-flop by performing comparison to determine whether or not the first value and the second value when the inputs to the plurality of scan chains are fixed to another of the “0” and the “1” by the switching circuit agree with each other.

2. The semiconductor integrated circuit according to claim 1 , comprising a logic BIST controller configured to perform diagnosis of a logic section of the semiconductor integrated circuit, wherein:
a test pattern for diagnosis of the logic section can be inputted to each of the plurality of scan chains; and
the logic BIST controller performs diagnosis of the logic section based on the test pattern.

3. The semiconductor integrated circuit according to claim 1 , wherein:
the switching circuit can perform switching so as to fix the inputs to the plurality of scan chains to the “0” or “1” or the respective first output data strings of the plurality of scan chains;
if the switching circuit fixes the inputs to the plurality of scan chains to the “0” or “1”, the first value is an expected value of the first output data string obtained as a result of a scan shift of the “0” or “1” after setting of the “0” or “1” in the inputs to the plurality of scan chains via the switching circuit, and the second value is a value of the second output data string obtained as a result of a scan shift of the “0” or “1” read and restored from the retention section; and
if the switching circuit fixes the inputs to the plurality of scan chains to the respective first output data strings of the respective scan chains, the first value is a value obtained as a result of a scan shift of the first output data strings of the respective scan chains via the switching circuit, and the second value is a value of the second output data string obtained as a result of a scan shift of the data read and restored from the retention section.

4. The semiconductor integrated circuit according to claim 1 , comprising:
a non-retention flip-flop scan chain including a non-retention flip-flop alone; and
a second switching circuit configured to switch a third output data string obtained as a result of a scan shift of data of the non-retention flip-flop scan chain, to a first predetermined value,
wherein the first value and the second value are each obtained as a result of a scan shift of a data string including the third output data string in the non-retention flip-flop scan chain.

5. The semiconductor integrated circuit according to claim 1 , wherein:
each of the plurality of scan chains includes a non-retention flip-flop; and
a second switching circuit configured to switch an output of the non-retention flip-flop to a first predetermined value is provided.

6. The semiconductor integrated circuit according to claim 1 , wherein:
one or two or more dummy flip-flops provided in a scan chain that is shorter than a maximum chain length from among the plurality of scan chains, the one or two or more dummy flip-flops making the maximum chain length and a chain length of the scan chain that is shorter than the maximum chain length equal to each other, are provided.

7. A diagnosis method for a semiconductor integrated circuit including a plurality of scan chains each including a retention flip-flop, the method comprising:
performing restoration of data saved in a retention section in the plurality of scan chains by reading the data from the retention section; and
after the restoration of the data, performing diagnosis of the retention flip-flop by performing comparison to determine whether or not a first value of a first output data string obtained as a result of a scan shift in each of the plurality of scan chains before the save of the data in the retention section and a second value of a second output data string obtained as a result of a scan shift of the data in each of the plurality of scan chains after the restoration agree with each other, wherein the data “0” or “1”;
the first value is an expected value of the first output data string obtained as a result of a scan shift of the “0” or “1” in the plurality of scan chains after setting of the “0” or “1” in the inputs to the plurality of scan chains via a switching circuit configured to perform switching of inputs to each of the plurality of scan chains to the “0” and “1”; and
the second value is a value of the second output data string obtained as a result of input of the data read and restored from the retention section to the plurality of scan chains and a scan shift of the data, the method further comprising, after performing diagnosis of the retention flip-flop by performing comparison to determine whether or not the first value and the second value when the inputs to the plurality of scan chains are fixed to one of the “0” and the “1” by the switching circuit agree with each other, performing diagnosis of the retention flip-flop by performing comparison to determine whether or not the first value and the second value when the inputs to the plurality of scan chains are fixed to another of the “0” and the “1” by the switching circuit agree with each other.

8. The diagnosis method for a semiconductor integrated circuit according to claim 7 , wherein:
the switching circuit can perform switching so as to fix the inputs to the plurality of scan chains to the “0” or “1” or the respective first output data strings of the plurality of scan chains;
if the switching circuit fixes the inputs to the plurality of scan chains to the “0” or “1”, the first value is an expected value of the first output data string obtained as a result of a scan shift of the “0” or “1” in the plurality of scan chains after setting of the “0” or “1” in the inputs to the plurality of scan chains via the switching circuit, and the second value is a value of the second output data string obtained as a result of input of the “0” or “1” read and restored from the retention section to the plurality of scan chains and a scan shift of the “0” or “1”; and
if the switchi

Assignees

• Toshiba Kk

Inventors

• Maekawa Tomoyuki

Classifications

• G06F11/267

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title

• G01R31/318575

  Power distribution; Power saving · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318533 Primary

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title

• G01R31/2851 Primary

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title