Method and apparatus for testing memory

Patent metadata

Field	Value
Publication number	US-2016111170-A1
Application number	US-201414556228-A
Country	US
Kind code	A1
Filing date	Nov 30, 2014
Priority date	Oct 16, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit. A portion of the system is placed in a low-power state for a predetermined period of time before data is read from the memory and retention of data by the memory while in the low-power state is determined.

First claim

1 . A method of testing operation of a memory of an integrated circuit, comprising:
loading a first scan chain of flip-flops with first data for testing data retention of the flip-flops; loading the memory with second data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit; placing at least a portion of the integrated circuit and the memory in a low-power state for a predetermined period of time; reading the second data from the memory; and determining retention of the second data by the memory in the low-power state based on the read data.

2 . The method of claim 1 , comprising:
loading the first scan chain and a second scan chain of flip-flops associated with the MBIST wrapper circuit with third data; initializing a logic portion of the integrated circuit to a known state based on the third data in the first and second scan chains; testing the logic portion of the integrated circuit in a normal power mode based on the third data in the first and second scan chains.

3 . The method of claim 1 , further comprising unloading the first data from the first scan chain and verifying data storage by the first scan chain based on the unloaded data.

4 . The method of claim 1 , further comprising outputting a signal indicative of correct retention of data by the memory when the read data is consistent with the second data loaded into the memory.

5 . The method of claim 1 , wherein the low power mode is a low leakage stop mode.

6 . The method of claim 1 , wherein in the low power mode, a clock to the logic portion of the system is stopped.

7 . The method of claim 1 , wherein the low power mode is a state retention power gating (SRPG) mode.

8 . The method of claim 1 , wherein the predetermined period of time is a greater of a flip-flop data retention requirement and a memory retention requirement.

9 . A system, comprising:
a memory for storing data; a memory built-in self-test (MBIST) wrapper circuit coupled to the memory for testing operation of the memory, wherein the MBIST wrapper circuit stores retention data in the memory; a scan chain of flip-flops having an input and an output, wherein the scan chain receives scan data via the input and stores the scan data therein; combinational logic; and a power management control (PMC) unit for controlling an operating voltage of at least the combinational logic, wherein the PMC unit initiates a low-power mode in which an operating voltage of at least the combinational logic is reduced for a predetermined period of time, and the MBIST wrapper circuit reads the retention data from the memory and determines retention of data by the memory based on the read data.

10 . The system of claim 9 , wherein the MBIST wrapper circuit comprises a plurality of flip-flops arranged to form a scan chain for initializing the combinational logic in a scan test mode.

11 . The system of claim 10 , wherein the scan test mode is performed at a system operating voltage.

12 . The system of claim 10 , wherein the flip-flops of the MBIST wrapper circuit are excluded from the scan chain in a low-power scan test mode for storing the retention data in the memory.

13 . The system of claim 9 , wherein at least a portion of the combinational logic is coupled to the memory such that one or more connections to the memory are operative at the reduced operating voltage in the low-power mode.

14 . The system of claim 9 , further comprising a state retention power gating (SRPG) unit arranged to test retention of data by the scan chain in the low-power mode.

15 . The system of claim 9 , wherein the MBIST wrapper circuit outputs a signal indicative of correct retention of data by the memory in the low-power mode.

16 . The system of claim 9 , wherein the retention of data by the memory is tested simultaneously with retention of data by the scan chain in the low-power mode.

17 . The system of claim 9 , wherein the low-power mode is a state retention power gating (SRPG) mode.

18 . An integrated circuit, comprising:
a memory for storing data; a memory test unit coupled to the memory for testing an operation of the memory; a plurality of flip-flops connected together into a serial scan chain; a power management control unit (PMCU) for controlling an operating voltage of a portion of the integrated circuit; and a test control unit (TCU) for loading scan data into the scan chain of flip-flops and causing the memory test unit to load retention data into the memory for a memory retention test, wherein the PMCU reduces the operating voltage of a logic portion of the system and the memory for a predetermined period of time, and the TCU determines the retention of the data in the memory after the reduction in the operating voltage.

Assignees

• Zhao Yunwu
• Wang Hao

Inventors

• Zhao Yunwu
• Wang Hao

Classifications

• G11C29/26 Primary

  Accessing multiple arrays (G11C29/24 takes precedence) · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G11C11/41

  forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger · CPC title

• G11C29/50016

  of retention · CPC title