Power gating control circuit for stably controlling data restoring

Patent metadata

Field	Value
Publication number	US-2016359472-A1
Application number	US-201615090896-A
Country	US
Kind code	A1
Filing date	Apr 5, 2016
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

Provided is a power gating control circuit for stably controlling data restoring. The power gating control circuit includes a retention circuit and a non-retention circuit. The retention circuit includes a first flip-flop, which stores or restores data of the first flip-flop in a power gating mode. The non-retention circuit includes a second flip-flop and a third flip-flop. The power gating control circuit performs initialization of data of the second flip-flop and the third flip-flop in the power gating mode, and an initialization operation of the non-retention circuit is controlled to be performed before data of the retention circuit is restored.

First claim

What is claimed is:

1 . A power gating control circuit, comprising:
a retention circuit including a first flip-flop, the retention circuit configured to store or restore data of the first flip-flop in a power gating mode; and a non-retention circuit including a second flip-flop and a third flip-flop, the non-retention circuit configured to,
initialize data of the second flip-flop in the power gating mode, and
initialize data of the third flip-flop in the power gating mode,
wherein the power gating control circuit is configured to initialize the non-retention circuit before the data of the first flip-flop in the retention circuit is restored.

2 . The power gating control circuit of claim 1 , wherein the first flip-flop of the retention circuit is configured to,
store the data of the first flip-flop before entering the power gating mode based on an output clock and a retention signal, restore the data of the first flip-flop after entering the power gating mode based on the output clock and the retention signal, and connect to the second flip-flop to receive an output of the second flip-flop.

3 . The power gating control circuit of claim 1 , wherein the power gating control circuit is configured to,
initialize the second flip-flop, the second flip-flop including a synchronous flip-flop, an operation of the second flip-flop synchronized with an output clock, and initialize the third flip-flop, the third flip-flop including an asynchronous flip-flop, an operation of the third flip-flop being independent of the output clock.

4 . The power gating control circuit of claim 3 , wherein the second flip-flop is configured to initialize the data in the second flip-flop based on the output clock, a reset signal, and an inactive power gating enable signal (PGEN),

5 . The power gating control circuit of claim 3 , wherein the third flip-flop is configured to,
operate independently of the output clock based on a reset signal, and initialize the data in the third flip-flop based on the reset signal and an inactive power gating enable signal (PGEN).

6 . A power gating control circuit, comprising:
a power management circuit (PMC) configured to supply power to a plurality of circuits; a clock management circuit (CMC) controllable by the PMC, the CMC configured to,
generate an output clock, and
operate in a retention mode;
a retention circuit configured to receive the output clock and operate in the retention mode; and a non-retention circuit configured to receive the output clock and initialize data in the non-retention circuit, wherein the PMC is configured to enter the CMC into the retention mode and enter the retention circuit into the retention mode independently of each other.

7 . The power gating control circuit of claim 6 , wherein the PMC is configured to,
release the retention circuit from the retention mode independently from the initialization of the non-retention circuit.

8 . The power gating control circuit of claim 7 , wherein the CMC is configured to,
suspend the output clock based on an inactive power gating enable signal (PGEN).

9 . The power gating control circuit of claim 8 , wherein the PMC is configured to,
provide a clock stop request signal to the CMC, the clock stop request signal requesting the output clock to be suspended.

10 . The power gating control circuit of claim 6 , wherein the PMC is configured to,
provide separate signals to the CMC and the retention circuit, respectively, for entering the retention mode.

11 . The power gating control circuit of claim 10 , wherein the PMC is configured to,
release the CMC from the retention mode before releasing the retention circuit from the retention mode.

12 . The power gating control circuit of claim 6 , wherein the retention circuit includes a first flip-flop, and the retention circuit is configured to,
perform one of storing and restoring of data in the retention circuit based on a retention signal and the output clock.

13 . The power gating control circuit of claim 9 , wherein the non-retention circuit is configured to respond to a reset signal and the output dock, and
the non-retention circuit includes,
a first flip-flop synchronized with the output clock, the first flip-flop configured to initialize data in the first flip-flop,
a second flip-flop independent of the output clock, the second flip-flop configured to initialize data in the second flip-flop, and
the first flip-flop is connected to a third flip-flop in the retention circuit such that an output of the first is provided to the third flip-flop.

14 . The power gating control circuit of claim 13 , wherein,
the first flip-flop is a synchronous flip-flop and does not include a reset terminal, and the second flip-flop is an asynchronous flip-flop and includes s terminal.

15 . The power gating control circuit of claim 6 , wherein the non-retention circuit is configured to,
initialize the data in the non-retention circuit before data of the retention circuit is restored.

16 . A power gating control circuit comprising:
a clock management circuit configured to,
generate an output clock signal based on a clock signal,
receive a clock stop request signal from a power management circuit (PMC),
suspend the output clock based on the clock stop request signal, and
forward a clock stop acknowledgment signal to the PMC based on the clock stop request signal; and
a retention circuit configured to perform one of storing and restoring of data in the retention circuit based on a retention signal and the output clock, the restoring of the data being based on the suspending of the output clock.

17 . The power gating control circuit of claim 16 , further comprising:
a non-retention circuit configured to initialize data in the non-retention circuit based on a reset signal from the PMC, the non-retention circuit configured to initialize the data in the non-retention circuit before the retention circuit restores the data of the retention circuit.

18 . The power gating control circuit of claim 17 , wherein,
the retention circuit includes a first flip-flop, and the non-retention circuit includes a second flip-flop and a third flip-flop, the second flip-flop configured to forward output values to the first flip-flop.

19 . The power gating control circuit of claim 18 , wherein,
the second flip-flop is a synchronous flip-flop and does not include a reset terminal, and the third flip-flop is an asynchronous flip-flop and includes the reset terminal.

20 . The power gating control circuit of claim 18 , wherein the third flip-flop is configured to operate independently of the output clock.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sangwoo

Classifications

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title