Multi-chip structure having flexible input/output chips

Patent metadata

Field	Value
Publication number	US-10397142-B2
Application number	US-201615050473-A
Country	US
Kind code	B2
Filing date	Feb 23, 2016
Priority date	Aug 17, 2015
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.

First claim

What is claimed is:

1. A multi-chip structure, comprising:
a switch system on chip (switch SOC) comprising a core circuit, a first multiplexer, and a first de-multiplexer;
a plurality of serializer/deserializer (SerDes) chips, positioned around the switch SOC, wherein at least two of the plurality of SerDes chips are manufactured by different semiconductor processes, and wherein the core circuit is manufactured by a different semiconductor process than that of at least one of the plurality of SerDes chips; and
a plurality of inter-chip interfaces, for connecting the switch SOC to the plurality of SerDes chips, respectively,
wherein a first SerDes chip of the plurality of SerDes chips comprises:
a second de-multiplexer, directly connected to the first de-multiplexer via a first inter-chip interface of the plurality of inter-chip interfaces, configured to convert first serial data to first parallel data and send the first parallel data to the switch SOC; and
a second multiplexer, directly connected to the first multiplexer via a second inter-chip interface of the plurality of inter-chip interfaces, configured to convert second parallel data from the switch SOC to second serial data and sending the second serial data to another chip.

2. The multi-chip structure of claim 1 , wherein the plurality of SerDes chips comprises at least three SerDes chips positioned at different sides of the switch SOC.

3. The multi-chip structure of claim 1 , wherein the plurality of SerDes chips comprises four SerDes chips, and the four SerDes chips are positioned at four sides of the switch SOC, respectively.

4. The multi-chip structure of claim 1 , wherein the plurality of SerDes chips supports at least two different standards.

5. The multi-chip structure of claim 4 , wherein the at least two different standards comprise a non-return-to-zero (NRZ) standard and a pulse-amplitude modulation (PAM) standard.

6. The multi-chip structure of claim 1 , wherein the switch SOC and the plurality of SerDes chips are within a single package.

7. The multi-chip structure of claim 1 , wherein the switch SOC and the plurality of SerDes chips are used in a physical network switch.

8. A multi-chip structure, comprising:
a system on chip (SOC) comprising a core circuit, a first multiplexer, and a first de-multiplexer;
at least three serializer/deserializer (SerDes) chips positioned at different sides of the SOC, wherein at least two of the at least three SerDes chips are manufactured by different semiconductor processes, and wherein the core circuit is manufactured by a different semiconductor process than that of at least one of the at least three SerDes chips; and
a plurality of inter-chip interfaces, for connecting the SOC to the at least three SerDes chips, respectively,
wherein a first SerDes chip of the at least three SerDes chips comprises:
a second de-multiplexer, directly connected to the first de-multiplexer via a first inter-chip interface of the plurality of inter-chip interfaces, configured to convert first serial data to first parallel data and send the first parallel data to the switch SOC; and
a second multiplexer, directly connected to the first multiplexer via a second inter-chip interface of the plurality of inter-chip interfaces, configured to convert second parallel data from the switch SOC to second serial data and sending the second serial data to another chip.

9. The multi-chip structure of claim 8 , wherein multi-chip structure comprises four SerDes chips, and the four SerDes chips are positioned at four sides of the SOC, respectively.

10. The multi-chip structure of claim 8 , wherein the at least three SerDes chips supports at least two different standards.

11. The multi-chip structure of claim 10 , wherein the at least two different standards comprise a non-return-to-zero (NRZ) standard and a pulse-amplitude modulation (PAM) standard.

12. The multi-chip structure of claim 8 , wherein the SOC and the at least three SerDes chips are within a single package.

13. The multi-chip structure of claim 8 , wherein the SOC and the at least three SerDes chips are used in a physical network switch.

14. A multi-chip structure, comprising:
a system on chip (SOC) comprising a core circuit, a first multiplexer, and a first de-multiplexer;
a plurality of input/output (IO) chips, positioned around the SOC, wherein at least two of the plurality of IO chips are manufactured by different semiconductor processes, and wherein the core circuit is manufactured by a different semiconductor process than that of at least one of the plurality of IO chips; and
a plurality of inter-chip interfaces, for connecting the SOC to the plurality of IO chips, respectively,
wherein a first IO chip of the plurality of IO chips comprises:
a second de-multiplexer, directly connected to the first de-multiplexer via a first inter-chip interface of the plurality of inter-chip interfaces, configured to convert first serial data to first parallel data and send the first parallel data to the switch SOC; and
a second multiplexer, directly connected to the first multiplexer via a second inter-chip interface of the plurality of inter-chip interfaces, configured to convert second parallel data from the switch SOC to second serial data and sending the second serial data to another chip.

15. The multi-chip structure of claim 14 , wherein the plurality of IO chips comprises four IO chips, and the four IO chips are positioned at four sides of the SOC, respectively.

16. The multi-chip structure of claim 14 , wherein the plurality of IO chips supports at least two different standards.

17. The multi-chip structure of claim 1 , wherein the different semiconductor processes by which the at least two of the plurality of SerDes chips are manufactured have different supply voltages.

18. The multi-chip structure of claim 8 , wherein the different semiconductor processes by which the at least two of the at least three SerDes chips are manufactured have different supply voltages.

19. The multi-chip structure of claim 14 , wherein the different semiconductor processes by which the at least two of the plurality of IO chips are manufactured have different supply voltages.

20. The multi-chip structure of claim 4 , wherein the at least two different standards comprise at least two different Ethernet standards.

21. The multi-chip structure of claim 10 , wherein the at least two different standards comprise at least two different Ethernet standards.

Assignees

• Mediatek Inc

Inventors

• Luo Yan-Bin
• Yin Hao-Hui
• Yu Chih-Ching
• Su Yao-Chun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H04L49/40 Primary

  Constructional details, e.g. power supply, mechanical construction or backplane · CPC title