Low power divide-by-seven divider

Patent metadata

Field	Value
Publication number	US-2016013794-A1
Application number	US-201414328671-A
Country	US
Kind code	A1
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

First claim

What is claimed is:

1 . A divide-by-seven divider, comprising:
a first module clocked with a clock input; and a second module coupled to the first module and clocked with an output of the first module, the first module and the second module being configured to divide the clock input by seven and to output the divided clock input.

2 . The divide-by-seven divider of claim 1 , wherein the first module is configured to store a count between 0 and 3 in a count cycle, the divide-by-seven divider further comprising a feedback module coupled between the first module and the second module and configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle.

3 . The divide-by-seven divider of claim 2 , wherein the first module is configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

4 . The divide-by-seven divider of claim 1 , wherein the first module comprises a first stage and a second stage, the first stage having a first stage input and a first stage output, the second stage having a second stage input and a second stage output, the second stage output being coupled to the first stage input, the first stage output being coupled to the second stage input, and wherein the second module comprises a third stage, the third stage having a third stage input and a third stage output, the third stage being clocked by the second stage output, the third stage output being coupled to the third stage input.

5 . The divide-by-seven divider of claim 4 , further comprising a feedback module having a feedback module input and a feedback module output, the feedback module input being coupled to the third stage output and the second stage output, the feedback module output being coupled to the second stage input.

6 . The divide-by-seven divider of claim 5 , wherein the first stage comprises a first D flip-flop, the second stage comprises a second D flip-flop, and the third stage comprises a third D flip-flop.

7 . The divide-by-seven divider of claim 5 , wherein the first module further comprises a first inverter coupled to the first stage output, a NOR gate coupled between the first inverter and the second stage input, and a second inverter coupled between the second stage output and the first stage input.

8 . The divide-by-seven divider of claim 7 , wherein the second module further comprises a third inverter coupled between the third stage output and the third stage input.

9 . The divide-by-seven divider of claim 8 , wherein the feedback module comprises a NAND gate receiving inputs from the second stage output and the third stage output, and a fourth inverter coupled to an output of the NAND gate, an output of the fourth inverter being coupled to an input of the NOR gate.

10 . The divide-by-seven divider of claim 4 , wherein an output of the divide-by-seven divider is the third stage output and the divide-by-seven divider has approximately a 40% duty cycle.

11 . The divide-by-seven divider of claim 4 , further comprising a fourth stage having a fourth stage input and a fourth stage output, the first stage having a first stage second output, the fourth stage being clocked by the first stage second output, the third stage output being coupled to the fourth stage input, the third stage output and the fourth stage output being coupled to an output of the divide-by-seven divider.

12 . The divide-by-seven divider of claim 11 , wherein the third stage output and the fourth stage output are coupled to an input of a NOR gate, an output of the NOR gate being the output of the divide-by-seven divider, wherein the divide-by-seven divider has approximately a 50% duty cycle.

13 . The divide-by-seven divider of claim 11 , wherein the first stage second output is a value stored in a master latch of the first stage.

14 . A method of operating a divide-by-seven divider, comprising:
storing a count between 0 and 3 in a count cycle within a first module, the first module being clocked with a clock input; clocking a second module with an output of the first module, the second module being coupled to the first module; causing, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle, the feedback module being coupled between the first module and the second module, the first module, the second module, and the feedback module being configured to divide the clock input by seven; and outputting the divided clock input.

15 . The method of claim 14 , wherein the first module is configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

16 . The method of claim 14 , wherein the first module comprises a first stage and a second stage, the first stage having a first stage input and a first stage output, the second stage having a second stage input and a second stage output, the second stage output being coupled to the first stage input, the first stage output being coupled to the second stage input, and wherein the second module comprises a third stage, the third stage having a third stage input and a third stage output, the third stage being clocked by the second stage output, the third stage output being coupled to the third stage input.

17 . The method of claim 16 , wherein the feedback module has a feedback module input and a feedback module output, the feedback module input being coupled to the third stage output and the second stage output, the feedback module output being coupled to the second stage input.

18 . The method of claim 16 , wherein an output of the divide-by-seven divider is the third stage output and the divide-by-seven divider has approximately a 40% duty cycle.

19 . The method of claim 16 , further comprising adjusting a duty cycle from less than 50% to approximately 50% by a fourth stage, the fourth stage having a fourth stage input and a fourth stage output, the first stage having a first stage second output, the fourth stage being clocked by the first stage second output, the third stage output being coupled to the fourth stage input, the third stage output and the fourth stage output being coupled to an output of the divide-by-seven divider.

20 . A divide-by-seven divider apparatus, comprising:
means for storing a count between 0 and 3 in a count cycle within a first module, the first module being clocked with a clock input; means for clocking a second module with an output of the first module, the second module being coupled to the first module; means for causing, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle, the feedback module being coupled between the first module and the second module, the first module, the second module, and the feedback module being configured to divide the clock input by seven; and means for outputting the divided clock input.

Assignees

• Qualcomm Inc

Inventors

• Su Wenjun
• Zhang Le
• Lee Chulkyu

Classifications

• H03K21/00 Primary

  Details of pulse counters or frequency dividers · CPC title

• H03K23/483

  with a base which is an odd number · CPC title