Semiconductor device, layout design method for the same and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10396030-B2
Application number	US-201816015465-A
Country	US
Kind code	B2
Filing date	Jun 22, 2018
Priority date	Nov 21, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first electrode including a first main portion, and a first extension that extends from the first main portion; and
a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion,
wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

2. The semiconductor device of claim 1 , wherein the first extension has a third depth shallower than the second depth.

3. The semiconductor device of claim 2 , the first depth and the third depth are substantially the same.

4. The semiconductor device of claim 1 , further comprising:
a second electrode including a second main portion and a second extension that extends from the second main portion,
wherein the dielectric layer electrically insulates the first electrode from the second electrode.

5. The semiconductor device of claim 4 , wherein the dielectric layer further surrounds the sidewall and the bottom surface of the second main portion, and
the second main portion includes a third portion having a third depth, and a fourth portion having a fourth depth deeper than the third depth.

6. The semiconductor device of claim 5 , wherein the second depth is substantially the same as the fourth depth.

7. The semiconductor device of claim 4 , wherein the first main portion and the second main portion extend in a first direction, and
the first extension and the second extension extend in a second direction intersecting with the first direction.

8. The semiconductor device of claim 7 , wherein the second portion of the first main portion extends in the second direction.

9. The semiconductor device of claim 7 , wherein the second portion of the first main portion overlaps the second extension in the second direction.

10. The semiconductor device of claim 1 , wherein the first main portion further includes a third portion having a third depth, and
the third depth is different from the first depth and is shallower than the second depth.

11. A semiconductor device comprising:
a first electrode including a first main portion extending in a first direction, and a first extension extending from the first main portion in a second direction intersecting with the first direction;
a second electrode including a second extension extending in the second direction; and
a dielectric layer surrounding a sidewall and a bottom surface of the first main portion,
wherein the first main portion includes a first portion having a first depth, and
the second extension has a second depth shallower than the first depth.

12. The semiconductor device of claim 11 , wherein the first main portion further includes a second portion having a third depth shallower than the first depth.

13. The semiconductor device of claim 12 , wherein the first portion and the second portion of the first main portion are alternately arranged along the first direction.

14. The semiconductor device of claim 12 , wherein the second depth and the third depth are substantially the same.

15. The semiconductor device of claim 11 , wherein the first portion of the first main portion overlaps the second extension in the second direction.

16. The semiconductor device of claim 11 , wherein the first portion of the first main portion overlaps the first extension in the second direction.

17. A semiconductor device comprising:
a first electrode including a first main portion extending in a first direction, and a plurality of first extensions extending from the first main portion in a second direction intersecting with the first direction;
a second electrode including a plurality of second extensions extending in the second direction; and
a dielectric layer disposed between each of the first extensions and each of the second extensions,
wherein each of the first extensions and each of the second extensions are arranged alternately along the first direction,
the first main portion includes a plurality of first portions having a first depth, and a plurality of second portions having a second depth deeper than the first depth, and
each of the second portions of the first main portion overlaps each of the second extensions in the second direction.

18. The semiconductor device of claim 17 , wherein each of the first portions of the first main portion overlaps each of the first extensions in the second direction.

19. The semiconductor device of claim 17 , wherein each of the first portions of the first main portion and each of the second portions of the first main portion are alternately arranged along the first direction.

20. The semiconductor device of claim 17 , wherein each of the second portions of the first main portion extends in the second direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Joon-Nyung
• Ahn Jeong Hoon

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title